Better Stimulus Generation Through AI

In today’s increasingly complex semiconductor landscape, verification engineers face unprecedented challenges in ensuring design correctness while meeting aggressive time-to-market demands. Questa One, Siemens EDA’s flagship verification solution, addresses these challenges through a three-pronged approach: delivering faster engines, enabling faster engineers, and requiring fewer workloads. By infusing artificial intelligence and machine learning algorithms throughout its comprehensive solution suite, Questa One’s optimized engines accelerate verification tasks with unprecedented speed, while its intelligent assistance transforms engineers into more efficient problem solvers.

Among Questa One’s productivity enhancers is its thoughtful integration of Large Language Models (LLMs), which serve as complementary tools to support experienced verification engineers. These AI models act as sophisticated assistants, helping engineers more quickly navigate documentation, explore potential solutions, and validate their approaches. However, the true value of LLMs emerges when wielded by engineers who bring solid verification expertise and critical thinking to the table.

Questa Portable Stimulus (QPS) is a particularly powerful enhancement to the Questa One simulation solution. QPS supports the Accellera Portable Stimulus Standard (PSS), enabling engineers to create abstract, reusable test intent that can be automatically translated into multiple verification environments, including:

• Universal Verification Methodology (UVM) sequences for simulation
• C code for embedded software testing
• Other platform-specific implementations

PSS eliminates the traditional need to manually recreate tests for different platforms and abstraction levels. QPS leverages an intelligent test generation engine that automatically explores the verification space defined by the abstract model, generating optimized test sequences that achieve coverage goals more efficiently than conventional directed or constrained-random approaches. This systematic approach not only reduces the engineering effort required to create and maintain test suites but also ensures consistent verification intent across the entire development flow, from IP to system level. The result is a more comprehensive verification process that requires significantly fewer resources while providing higher confidence in the design’s correctness.