FPGA Functional Verification Trend Report - 2024

Alarmingly, 87 percent of projects reported non-trivial bug escapes into production, emphasizing the need for robust pre-lab verification practices. The report also explores the adoption of verification languages, formal technologies and methodologies, revealing trends that suggest a shift toward greater verification maturity. This study underscores the urgent need for connected, data-driven and scalable verification solutions to meet the demands of modern FPGA projects.

This report examines the trends in functional verification for the field programmable gate array (FPGA) market segments identified in the 2024 Wilson Research Group study. This study continues a series of industry analyses conducted over the past two decades.^1,2,3,4 For the 2024 study, we have distinguished between FPGA and IC/ASIC functional verification trends, with this report concentrating on the former.

A. The Global FPGA Semiconductor Market

IBS estimates that the global semiconductor market was valued at $547 billion in 2021. While the market faced a decline to approximately $526.8 billion in 2023 due to economic challenges and reduced demand, it is projected to recover strongly, reaching a value of $635 billion by 2025.5 The FPGA segment, excluding IC/ASIC/Memories, was estimated at $8.27 billion in 2023 and continues to grow, driven by accelerating demand for advanced technologies. Key growth drivers include data center computing, networking, storage and next-generation communication systems.

FPGAs have historically offered two distinct advantages over ASICs. First, their low non-recurring engineering (NRE) costs make them cost-effective for low-volume production. Second, their flexibility and rapid prototyping capabilities significantly reduce development schedules by enabling extensive verification and validation cycles in the lab. More recently, FPGAs have also demonstrated performance advantages in specific accelerated applications, such as AI neural networks, by leveraging hardware parallelism.

The IC/ASIC market in the mid- to late-2000s faced significant challenges in addressing increasing verification complexity. Similarly, today’s FPGA market is experiencing growing pains as projects contend with the demands of modern designs. While the limitations of current FPGA verification processes contribute to challenges, much of the issue stems from the maturity level of FPGA projects. Many FPGA teams prioritize minimal pre-lab verification, aiming to reach the lab quickly for design validation – a strategy that was effective for simpler FPGAs in the past but is increasingly impractical for today’s complex devices, particularly SoC-class FPGAs. This paper examines these dynamics and quantifies the impact on verification outcomes, including the prevalence of nontrivial bug escapes into production.

B. Study Background

The results presented in this report continue a series of nine industry studies on functional verification conducted from 2007 to the present 2024 study.^3,4 Each of these studies was modeled after the 2002 and 2004 studies by Collett International Research, Inc. studies.^1,2

For our study, we constructed a randomized sampling frame from multiple acquired industry lists, covering all regions of the world and relevant electronics industry market segments. Notably, we excluded our account team’s customer list to prevent vendor bias in the results. While we designed the study questions and analyzed the results, we commissioned Wilson Research Group to execute the study. After cleaning the data to remove inconsistent, incomplete, or random responses, the final sample size consisted of 597 eligible participants (n=597).