The Fundamental Power States for UPF Modeling and Power Aware Verification

The IEEE 1801-2015 specifies the new semantics for power states through the “add_power_state” UPF com­mand. This new construct primarily allows incremental refinement of power states for power domains and its associated supply sets. The refinement concept originated from the fundamental conceptual set of power states termed as indefinite, definite and deferred power states.[1] In practice we perceived these concep­tual sets and extended them as foundation of for static and dynamic verification methodologies.

Our approach shows validation procedures for UPF strategies. With design examples and case studies we also demonstrate how to achieve power aware verifica­tion closure with state and transition coverage, as well as state cross coverage of power domains and supply sets, in more flexible and controllable ways. The realiza­tion of the power state concept allows us to probe further into the power management components for design and IP integration at different levels of design, from the RTL to PG-netlist.

UPF is the power management methodology that facili­tates adopting different power dissipation reduction techniques, like power gating and low-power standby etc. and allow to formalize the modeling and mapping of power specification on to a design. The fundamental constituent parts for UPF constructions are broadly based on the following categories.

List 1. Fundamental constituent parts for UPF constructions

• Design scopes for the UPF
• Power domains
• Power domain interfaces and power domain boundaries
• Power supply and power supply networks
• Primary power and primary ground
• Power states and modes of power operations
• Power strategies

These rudimentary constituent parts of UPF are further augmented with design or HDL construct parameters as shown in List 1. Specifically, the design scope may include the hierarchical top design module or instance name and power domain confined hierarchical instance paths to define the boundary of the domain. The power strategies – for example isolations, level-shifters, power switches, retention flops etc. also refers design or HDL instances, ports, and nets for inferring or inserting corresponding cells and connecting control signals. However, strategies are based on the power states of the power supplies of the power domains. Obviously because an ISO may be required between a relatively OFF and ON power domains to isolate unknown value propagation; however, the ON or OFF states of the corresponding power domains are revealed through the power states or the power supplies of the domains.

These power states are defined through the UPF add_ power_state command that defines one or more power states of an object. Objects are the rudimentary parts of the power supply architecture. Design elements such as supply sets, power domains, design groups, design models, and design instances are collectively known as objects.^2,3 The new power states definition completely replaces the conventional power state table (PST), treating it as legacy,^1,2 and it enables multiple possible combinations of power states and their transition mod­els for the objects at any level of design abstraction. The incremental refinement features allow engineers to define new power states either on its original or on its derivatives entities for any object. Such power states provide more flexibility to represent different opera­tional modes of a design with more controllability.