MARLUG - 2024
User2User Mid-Atlantic is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools.
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Session Slides
Session Title
Abstract
Slides
Questa Equivalent FPGA: Assuring FPGA Integrity
- Martin Rowe | Siemens EDA, Brandon Huynh | Northrop GrummanFormal verification has been a popular design flow among ASIC designers as a proven method to perform design implementation verification. The Questa Equivalent RTL software allows FPGA designers to utilize equivalency checking principles on FPGAs with access to vendor libraries allowing proper analysis of low-level primitives e.g. native RAM and DSP elements. The tool was recently explored at Northrop Grumman to verify the functional equivalence of firmware targeted to FPGAs from different vendors such as AMD and Intel. While we discovered a few issues and bugs that are actively being resolved during our exploration, we found that Questa Equivalent RTL’s ability to support FPGA device primitives to be incredibly useful and unique among similar industry tools. For a variety of firmware circuits, Questa Equivalent RTL successfully proved the equivalence of the designs as hosted on FPGAs from different vendors. PDF Challenges of Multiple FPGA Tool Flow Verification
- Paul Bobko | Westinghouse ElectricThis session will examine the challenges of utilizing common RTL for different FPGA targets. Each FPGA target requires a different tool flow, therefore verification of each tool flow is necessary in determining functional accuracy. Traditionally, simple functional verification has been sufficient to guard against tool flow issues affecting the FPGA design. However, functional safety requirements necessitate a more robust verification process. Equivalency checking ensures that a tool flow defect is not realized in the final product. PDF Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics
- Austin Mam | Siemens EDAThis session will cover Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency. PDF Universal Verification Methodology (UVM): VIP Challenges & Effective Deployment Guide
- Jeffrey Jacobson, Marc Jurchak | L3HarrisThis session will give a brief overview of Universal verification methodology (UVM), introduce Verification Intellectual Property (VIP) and cover benefits for using industry standard VIPs. We will delve into challenges faced with deploying VIPs, including protocol complexities, training, and critically tailoring/tuning the VIP for your target interface for FPGAs or ASICs. We present step-by-step flowchart to plan, budget, train, ramp-up, pre-validate, adopt, and successfully deploy VIPs on projects. PDF