1. Session Registration

    Session Registration

    Date and Time

    • Wednesday, February 19th
    • 8:00 AM US/Pacific
  2. Session Overview

    Security and safety policies across various domains such as aerospace and defense, embedded security, and automotive safety have been updated to require an FPGA verification chain spanning from verified HDL source, extending throughout the FPGA implementation tool chain, and culminating with the FPGA bitstream.

    Key topics to be explored in this session include:

    • Discussion of security and safety guidance for FPGA equivalence checking and bitstream verification
    • Identification of a joint equivalence checking and bitstream verification tool chain providing compliance solutions
    • Implementation defects necessitating a joint verification flow

    Whether you are an experienced verification engineer or are simply looking to expand your knowledge of innovative safety and security compliance methods, this seminar will equip you with comprehensive solutions to tackle current and emerging requirements for FPGA designs.

    What You Will Learn

    • Why expanding your verification to the bitstream is needed?
      • Introduction to Assurance and Safety guidance for FPGA bitstream verification
      • Example of applicable implementation defects
    • Industry first equivalence checking tool flow for RTL to FPGA bitstream compliance

    Who Should Attend

    • FPGA Design Engineers
    • FPGA Verification Engineers
    • Trust / Assurance Engineers
    • Safety Engineers
    • Security Engineers

    Products Covered

    • Siemens Questa Equivalent FPGA
    • Graf Research Enverite PV-Bit