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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
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      • Package/Organization
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      • SystemVerilog Guidelines
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      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Visualizer Debug - October 27th
      • Fault Campaign Management - October 29th
      • Events Calendar

    • On Demand Seminars

      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
      • Bottoms-Up Safety Analysis
      • Memory Modeling - DDR VIP
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
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    • Mentor Training Center

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    • Mentor Learning Center

      • SystemVerilog Fundamentals
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      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Technical Resources

Verification Horizons Articles

SystemVerilog:

  • Understanding the SVA Engine Using the Fork-Join Model
  • SVA Alternative for Complex Assertions
  • An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench
  • Reuse MATLAB® Functions and Simulink® Models in UVM Environments with Automatic SystemVerilog DPI Component Generation
  • Merging SystemVerilog Covergroups by Example
  • SVA in a UVM Class-based Environment
  • Bringing Verification and Validation under One Umbrella
  • Don't Forget the Little Things That Can Make Verification Easier
  • Assertions Instead of FSMs/logic for Scoreboarding and Verification
  • Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features
  • Relieving the Parameterized Coverage Headache
  • Better Living Through Better Class-Based SystemVerilog Debug

Debug:

  • Parallel Debug: A Path to a Better Big Data Diaspora
  • Certus™ Silicon Debug: Don't Prototype Without It
  • On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
  • Increase Verification Productivity with Questa® UVM Debug
  • Questa® Visualizer Debug: Class-based Testbench Debugging using a New School Debugger – Debug This!

Verification IP:

  • PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA Application
  • Coverage Driven Verification of NVMe Using Questa® VIP (QVIP)
  • SATA Specification 3.3 Gaps Filled by SATA QVIP
  • Configuring Memory Read Completions Sent by PCIe® QVIP
  • Step-by-step Tutorial for Connecting Questa® VIP into the Processor Verification Flow
  • MIPI® CSI2 TX IP Verification Using Questa® VIPs
  • Converting Legacy USB IP to a Low Power USB IP
  • USB Type-C Verification: Challenges and Solution
  • Simplifying HDCP Verification Using Questa® VIP
  • Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
  • MIPI C-PHY™: Man of the Hour
  • Total Recall: What to Look for in a Memory Model Library
  • Nine Effective Features of NVMe® Questa® Verification IP to Help You Verify PCIe® Based SSD Storage
  • DO-254 Compliant UVM VIP Development
  • Memories Are Made Like This
  • QVIP Provides Thoroughness in Verification
  • Resolving the Limitations of a Traditional VIP for PHY Verification
  • Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide
  • Fast Track to Productivity Using Questa® Verification IP
  • Cache Coherent Interface Verification IP
  • Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench
  • MIPI LLI Verification using Questa Verification IP
  • Caching in on Analysis
  • DDR SDRAM Bus Monitoring using Mentor Verification IP
  • Maximum Productivity with Verification IP
  • Verifying High Speed Peripheral IPs
  • NoC Generic Scoreboard VIP

UVM:

  • Fun with UVM Sequences - Coding and Debugging
  • UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs
  • Simplifying Assertion Validation Using UVM Callbacks
  • Complex Addressable Registers in Mission Critical Applications
  • UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
  • UVM Tips and Tricks
  • INs and OUTs of CAN Verification—A Comprehensive UVM-based Solution
  • Solve UVM Debug Problems with the UVM Vault
  • Extending UVM Verification Models for the Analysis of Fault Injection Simulations
  • No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model
  • An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench
  • A Generic UVM Scoreboard
  • Small, Maintainable Tests
  • Please! Can Someone Make UVM Easier to Use?
  • UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment
  • Dealing With UVM and OVM Sequences
  • Making it Easy to Deploy the UVM
  • Flexible UVM Components: Configuring Bus Functional Models
  • Monitors, Monitors Everywhere – Who Is Monitoring the Monitors?
  • OVM to UVM Migration, or "There and Back Again: A Consultant's Tale"
  • Three Steps to Unified SoC Design and Verification
  • On the Fly Reset
  • Relieving the Parameterized Coverage Headache

Verification Management & Metrics

  • An Open Data Management Tool for Design and Verification
  • Verification Planning with Questa® Verification Management
  • Increased Efficiency with Questa® VRM and Jenkins Continuous Integration
  • Increasing Verification Productivity Through Functional Coverage Management Automation
  • QVM: Enabling Organized, Predictable, and Faster Verification Closure
  • ST-Ericsson Speeds Time to Functional Verification Closure with Questa Verification Platform
  • Mentor Has Accellera's Latest Standard Covered
  • Automation Management: Are You Living a Scripted Life?
  • Efficient Project Management and Verification Sign-off Using Questa Verification Management?
  • Process Management: Are You Driving in the Dark with Faulty Headlights?
  • Data Management: Is There Such a Thing as an Optimized Unified Coverage Database?

FPGA:

  • Addressing VHDL Verification Challenges with OSVVM
  • FPGA Verification Challenges and Opportunities
  • Best Practices for FPGA and ASIC Development
  • Reuse MATLAB® Functions and Simulink® Models in UVM Environments with Automatic SystemVerilog DPI Component Generation
  • Best Practices for FPGA and ASIC Development
  • Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs

Low Power

  • Effective Elements Lists and the Transitive Nature of UPF Commands
  • A New Approach to Low-Power Verification: Power Aware Apps
  • Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs
  • Part I: Power Aware Static Verification - From Power Intent to Microarchitectural Checks of Low-Power Designs
  • PA GLS: The Power Aware Gate-level Simulation
  • Understanding the UPF Power Domain and Domain Boundary
  • Artifacts of Custom Checkers in Questa® Power Aware Dynamic Simulation
  • Power Aware Libraries: Standardization and Requirements for Questa® Power Aware
  • Successive Refinement: A Methodology for Incremental Specification of Power Intent
  • PowerAware RTL Verification of USB 3.0 IPs
  • Taming Power Aware Bugs with Questa®
  • The Evolution of UPF: What's Next?
  • Evolution of UPF: Getting Better All the Time

 

  

Portable Stimulus:

  • Bridging the Portability Gap for UVM SPI VIP Core Reuse From IP to Sub-System and SoC Using Portable Stimulus
  • Exercising State Machines with Command Sequences
  • Designing A Portable Stimulus Reuse Strategy
  • Creating Tests the PSS Way in SystemVerilog
  • Auto-Generating Implementation-Level Sequences for PSS
  • Selecting a Portable Stimulus Application Focal Point
  • Building a Better Virtual Sequence with Portable Stimulus
  • Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
  • Make Your Constraints More Dynamic with Portable Stimulus
  • Getting Generic with Test Intent: Separating Test Intent from Design Details with Portable Stimulus
  • Smoothing the Path to Software-Driven Verification with Portable Stimulus
  • Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow
  • Automating Tests with Portable Stimulus from IP to SoC Level
  • Bridging UVM to the Portable Stimulus Standard with Questa® inFact
  • Improving Performance and Verification of a System Through an Intelligent Testbench
  • Saving Time and Improving Quality with a Specification to Realization Flow
  • A New Stimulus Model for CPU Instruction Sets
  • Intelligent Testbench Automation with UVM and Questa®
  • Portable VHDL Testbench Automation with Intelligent Testbench Automation
  • Software-Driven Testing of AXI Bus in a Dual Core ARM® System
  • Power Up Hardware/Software Verification Productivity
  • Is Intelligent Testbench Automation For You?
  • Automated Generation of Functional Coverage Metrics for Input Stimulus
  • Targeting Internal-State Scenarios in an Uncertain World

Safety Critical / ISO 26262

  • Effective Validation Method of Safety Mechanism Compliant with ISO 26262
  • SystemC FMU for Verification of Advanced Driver Assistance Systems
  • ISO 26262 Fault Analysis – Worst Case is Really the Worst
  • Getting ISO 26262 Faults Straight
  • It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
  • EDA Support for Functional Safety — How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety
  • Will Safety Critical Design Practices Improve First Silicon Success?
  • A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products

Emulation:

  • Why Hardware Emulation Is Necessary to Verify Deep Learning Designs
  • Three Main Components to Look for in Your Emulation Platform
  • Emulation – A Job Management Strategy to Maximize Use
  • 24 x 7 Productivity: Veloce® Enterprise Server App Does the Job
  • Accelerating Networking Products to Market
  • Hardware Emulation: Three Decades of Evolution—Part III
  • Hardware Emulation: Three Decades of Evolution – Part II
  • Hardware Emulation: Three Decades of Evolution
  • Emulation Based Approach to ISO 26262 Compliant Processors Design
  • Optimizing Emulator Utilization
  • Simulation + Emulation = Verification Success
  • Bringing Verification and Validation under One Umbrella
  • Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces

CDC & Formal Verification:

  • Formal Is The “New Normal” - Deploy These FV Apps In Your Next Project
  • Using Questa® SLEC to Speed Up Verification of Multiple HDL Outputs
  • Formal Verification of RISC-V® Processors
  • Deadlock Prevention Made Easy with Formal Verification
  • Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
  • Formal Bug Hunting with “River Fishing” Techniques
  • Ten Rules to Successfully Deploy Formal
  • Formal Apps Take the Bias Out of Functional Verification
  • It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
  • Comprehensive CDC Verification with Advanced Hierarchical Data Models
  • RTL Glitch Verification
  • Reset Verification in SoC Designs
  • Debugging Inconclusive Assertions and a Case Study
  • Formal Verification: Not Just for Control Paths
  • RTL CDC Is No Longer Enough — How Gate-Level CDC Is Now Essential to First Pass Success
  • How Formal Techniques Can Keep Hackers from Driving You into a Ditch
  • Minimizing Constraints to Debug Vacuous Proofs
  • Evolving the Use of Formal Model Checking in SoC Design Verification
  • Functional Coverage Development Tips: Do's and Don'ts
  • Formal and Assertion-Based Verification of MBIST MCPs
  • Starting Formal Right from Formal Test Planning
  • Life Isn't Fair, So Use Formal
  • Confidence in the Face of the Unknown: X-state Verification
  • Using Formal Analysis to "Block and Tackle"
  • The Formal Verification of Design Constraints
  • The Top Five Formal Verification Applications

DO-254

  • Simplified UVM for FPGA Reliability: UVM for "Sufficient Elemental Analysis" in DO-254 Flows
  • Physical Verification of FPGAs in Accordance with an Aerospace DO-254 Methodology Flow
  • Simplified UVM for FPGA Reliability: UVM for "Sufficient Elemental Analysis" in DO-254 Flows
  • Complex Signal Processing Verification under DO-254 Constraints
  • Verifying Airborne Electronics Hardware: Automating the Capture of Assertion Verification Results for DO-254
  • DO-254 Testing of High Speed FPGA Interfaces

Verification Techniques:

  • Extending SoC Design Verification Methods for RISC-V Processor DV
  • Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip
  • AI-Based Sequence Detection
  • Verify Thy Verifyer
  • A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs
  • Automation and Reuse in RISC-V Verification Flow
  • Complementing Functional Verification Through the Use of Available Timing Information
  • How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology
  • First Time Unit Testing Experience Report with SVUnit
  • The Verification Academy Patterns Library
  • Reusable Verification Framework
  • Does Design Size Influence First Silicon Success?
  • Unit Testing Your Way to a Reliable Testbench
  • Accelerating RTL Simulation Techniques
  • Hey You, Design Engineer!
  • Use of Iterative Weight-Age Constraint to Implement Dynamic Verification Components
  • Using Mentor Questa® for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
  • Interviewing a Verification Engineer
  • Non-invasive Software Verification Using Vista Virtual Platforms
  • The Need for Speed: Understanding Design Factors that Make Multi-core Parallel Simulations Efficient
  • System Level Code Coverage using Vista Architect and SystemC
  • VHDL-2008: Why It Matters

AMS:

  • Simplifying Mixed-Signal Verification
  • Stories of an AMS Verification Dude: Model Shmodel
  • Stories of an AMS Verification Dude: Putting Stuff Together
  • AMS Verification for High Reliability and Safety Critical Applications
  • Improving Analog/Mixed-Signal Verification Productivity

Success Stories

Clock-Domain Crossing:

  • Northwest Logic Automates CDC and RDC Verification Using Questa CDC and Questa Reset Check

Debug:

  • Visualizer™ Debug Environment reduces Debug time and Increases Productivity for Brocade®
  • Adding Clarity to the Debug Picture at Pixelworks

Formal Verification:

  • How Microsemi Uses Questa Formal Connectivity Check to Improve Quality and Productivity
  • Cypress Adopts Questa Formal Apps to Create Pristine IP

Verification Patterns

Environment Patterns:

  • BFM-Proxy Pair Pattern
  • Component Configuration Pattern
  • Dual Domain Hierarchy Pattern
  • Environment Layering Pattern
  • Façade Pattern
  • Parameterized UVM Tests Pattern
  • Resource Sharing Pattern
  • SW-HW Pipe Pattern
  • Utility Pattern

Order Property Patterns:

  • Precedence Chain Property Pattern
  • Precedence Property Pattern
  • Response Chain Property Pattern
  • Response Property Pattern
  

Stimulus Patterns:

  • Layering Sequence Pattern
  • Strategy Pattern

Analysis Patterns:

  • BFM Notification Pattern
  • Walking Pattern

Occurrence Property Patterns:

  • Absence Property Pattern
  • Bounded Existence Property Pattern
  • Existence Property Pattern
  • Forbidden Sequence Property Pattern
  • Universality Property Pattern

Technical Papers

UVM:

  • Transaction Recording Anywhere Anytime
  • UVM IEEE Shiny Object
  • UVM and C Tests - Perfect Together
  • UVM Sans UVM: An Approach to Automating UVM Testbench Writing
  • Are You Smarter Than Your Testbench? With a Little Work You Can Be
  • Slaying the UVM Reuse Dragon
  • Beyond UVM Registers - Better, Faster, Smarter
  • Sequence, Sequence on the Wall – Who's the Fairest of Them All?
  • Monitors, Monitors Everywhere – Who Is Monitoring the Monitors
  • Seven Separate Sequence Styles Speed Stimulus Scenarios
  • Boosting Simulation Performance of UVM Registers in High Performance Systems
  • Transaction-Level Friending: An Open-Source, Standards-Based Library for Connecting TLM Models in SystemC and SystemVerilog
  • Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program

SystemVerilog:

  • Using Strong Types in SystemVerilog Design and Verification Environments
  • The Missing Link: The Testbench to DUT Connection
  • DPI Redux. Functionality. Speed. Optimization
  • No RTL Yet? No Problem - UVM Testing a SystemVerilog Fabric Model
  • Introspection Into SystemVerilog Without Turning It Inside Out
  • Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse
  • Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI

Verification IP:

  • Coverage Driven Verification of NVMe Using Questa VIP
  • Five Common Pitfalls To Avoid While Verifying PCIe Based NVMe Controllers
  • Total Recall - What to Look for in a Memory Model Library
  • Verification IP Stimulus APIs - Are They Really Easy to Use?
  • Extending a Traditional VIP to Solve PHY Verification Challenges
  • Verifying Display Standards–A Comprehensive UVM-based Verification IP Solution
  • Using Test-IP Based Verification Techniques in a UVM Environment

Debug:

  • Debug This! Class-based testbench debugging with Visualizer
  • Full-Featured SOC Debug Cross-Triggering

Low Power:

  • A New Approach to Low-Power Verification: Power Aware Apps
  • Moving Beyond Assertions: An Innovative Approach to Low-Power Checking Using UPF Tcl Apps
  • Reusable UPF: Transitioning from RTL to Gate Level Verification
  • Effective Elements List and Transitive Natures of UPF Commands
  • Low Power Apps: Shaping the Future of Low Power Verification
  • UPF Information Model: The Future of Low-Power Verification Today
  • Low Power Coverage: The Missing Piece in Dynamic Simulation
  • Random Directed Low-Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure
  • Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
  • The Fundamental Power States for UPF Modeling and Power Aware Verification
  • Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification
  • Advanced Verification of Low Power Designs
  • To Retain or Not to Retain: How Do I Verify the State Elements of My Low Power Design?
  • Low Power Design and Verification Techniques

Portable Stimulus:

  • Results Checking Strategies with Portable Stimulus
  • Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy
  • Managing and Automating HW/SW Tests from IP to SoC
  • Boost Verification Results by Bridging the Hardware/Software Testbench Gap
  • Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
  • UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process

Coverage:

  • Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify Use Models
  • Debugging Functional Coverage Models: Get the Most Out of Your Cover Crosses
  • Coverage Data Exchange Is No Robbery…Or Is It?
  • UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process
  • Cross Coverage of Power States

Formal Verification:

  • Formal Apps Take the Bias Out of Functional Verification
  • Reset Verification in SoC Designs
  • Formal Techniques for Optimizing ISO 26262 Fault Analysis
  • Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking
  • Questa® CoverCheck: An Automated Code Coverage Closure Solution
  • Register Verification: Do We Have Reliable Specification?
  • Is Your Power Aware Design Really X-Aware?

CDC and RDC:

  • A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic
  • Clock-Domain Crossing Challenges in Latch Based Designs
  • Comprehensive CDC Verification Using Advanced Hierarchical Data Models
  • Systematic Speedup Techniques for Functional CDC Verification Closure
  • Power Aware CDC Verification of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts
  • Accelerating CDC Verification Closure on Gate-Level Designs
  • Five Steps to Quality CDC Verification

Simulation:

  • Efficient Modeling Styles and Methodology for Gate-Level Design Verification
  • The Big Brain Theory: Visualizing SoC Design and Verification Data
  • Boosting Regression Throughput by Reusing Setup Phase Simulation
  • The Need For Speed: Understanding Design Factors That Make Multi-Core Parallel Simulations Efficient
  • Traffic Profiling and Performance Instrumentation For On-Chip Interconnects

Metrics:

  • Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology
  • So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results

Verification Management:

  • Improving Verification Predictability and Efficiency Using Big Data
  • Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
  • Bringing Regression Systems into the 21st Century
  • Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?

Analog/Mixed-Signal:

  • Interpreting UPF For A Mixed-Signal Design Under Test
  • Equivalence Validation of Analog Behavioral Models

Functional Safety:

  • Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task
  • Achieving Functional Safety for Autonomous Vehicle SoC Designs
  • Using An Automated Fuzzing Test Of A Virtual Prototype To Eliminate ECU Security Vulnerabilities
  • Assessing the ModelSim and Questa Tools for Use in DO-254 Projects?
  • Understanding DO-254 and Solutions to Facilitate Compliance
  • Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools

FPGA Verification:

  • FPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertion

Emulation:

  • From Simulation to Emulation – A Fully Reusable UVM Framework
  • UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up
  • Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning
  • UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up
  • Off to the Races with Your Accelerated SystemVerilog Testbench
  • Optimizing Emulator Utilization
  • Power - Usage Shift Leads to Methodology Shift
  • Exploring New Uses for the Veloce DFT App, Fault Coverage and Power Analysis
  • Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
  • Veloce System-Level Power Analysis and Verification
  • Virtual Devices for Protocol-Specific Host and Peripheral Interfaces

OVM:

  • Parameters and OVM - Can't They Just Get Along?
  • One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies

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