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1627 Results

• Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

  Webinar - May 22, 2024 by Farhad Ahmed

  In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

• Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

  Resource (Slides) - Apr 16, 2024 by Rich Edelman

  In this webinar we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size.

• Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

  Webinar - Apr 16, 2024 by Rich Edelman

  Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.

• Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench

  Seminar - Apr 04, 2024 by Salil Pandit, Robert Rice - Siemens EDA

  It's always challenging for Design-Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this presentation, we walk through 5 concrete steps you can take to fully understand a “new to you” UVM testbench.

• Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench

  Resource (Slides) - Apr 04, 2024 by Salil Pandit, Robert Rice - Siemens EDA

  It's always challenging for Design-Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this presentation, we walk through 5 concrete steps you can take to fully understand a “new to you” UVM testbench.

• Why and How We Migrated from In-house Regression Management and Coverage flow to Verification IQ

  Seminar - Apr 04, 2024 by Avinash Agrawal - Siemens EDA

  In this session we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.

• Why and How We Migrated from In-house Regression Management and Coverage flow to Verification IQ

  Resource (Slides) - Apr 04, 2024 by Avinash Agrawal - Siemens EDA

  In this session we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.

• How and Why We Adopted Questa Core in the Development of Quantum Computers

  Seminar - Apr 04, 2024 by Jan Marjanovic - Atom Computing

  This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.

• How and Why We Adopted Questa Core in the Development of Quantum Computers

  Resource (Slides) - Apr 04, 2024 by Jan Marjanovic - Atom Computing

  This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.

• How We Use PCIe Verification IP Across Multiple Projects

  Seminar - Apr 04, 2024 by Weiping Guo - Marvell

  In this session we will discuss how Marvell delivers successful products and drives the market by with a structured design and verification methodology that reflects this philosophy. Specifically, we will dive deep into one of the most complex protocols: PCIe IP and the related testbench architecture; and how we adopted Siemens’ PCIe Avery Verification IP.

• How We Use PCIe Verification IP Across Multiple Projects

  Resource (Slides) - Apr 04, 2024 by Weiping Guo - Marvell

  In this presentation we will discuss how Marvell delivers successful products and drives the market by with a structured design and verification methodology that reflects this philosophy. Specifically, we will dive deep into one of the most complex protocols: PCIe IP and the related testbench architecture; and how we adopted Siemens’ PCIe Avery Verification IP.

• Customer Case Studies with AI/ML in Verification

  Seminar - Apr 04, 2024 by Karim Ameziane - Siemens EDA

  In this session we will share some results from our customer partnerships on how AI/ML is helping them with particular verification needs. The common thread: in order to apply advanced ML techniques to bring more value to verification, we show how to focus on building data assets that will put a verification team on the path to ML success.

• Customer Case Studies with AI/ML in Verification

  Resource (Slides) - Apr 04, 2024 by Karim Ameziane - Siemens EDA

  In this session we will share some results from our customer partnerships on how AI/ML is helping them with particular verification needs. The common thread: in order to apply advanced ML techniques to bring more value to verification, we show how to focus on building data assets that will put a verification team on the path to ML success.

• The Importance of Simulation in the Pursuit of Absolute Speed!

  Resource (Verification Horizons Blog) - Apr 02, 2024 by Sunil Sahoo

  I recently had an opportunity to talk to someone who worked in the high-frequency trading (HFT) sector a few years ago. I wanted to know how they performed their functional simulations. If you know anything about HFT or low-latency trading, you know that those engineers are very secretive and don’t divulge a lot of details about what their FPGA design-verification process entails.

• Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

  Resource (Slides) - Mar 27, 2024 by Rick Koster

  Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity.

• Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

  Webinar - Mar 27, 2024 by Rick Koster

  This session will describe a reliable formal-based method to manage Xs in GLS. It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator.

• In Memoriam: Chris Spear

  Resource (Verification Horizons Blog) - Mar 14, 2024 by Tom Fitzpatrick

  Our friend and colleague Chris Spear passed away suddenly. He was a long-time veteran of our industry and was known and respected by many.

• New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

  Resource (Slides) - Mar 14, 2024 by Atul Sharma

  In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

• New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

  Webinar - Mar 14, 2024 by Atul Sharma

  In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

• Get your free copy of the IEEE 1800-2023 SystemVerilog LRM

  Resource (Verification Horizons Blog) - Mar 04, 2024 by Dave Rich

  At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog standard. After a year of two rounds of balloting, the final revision is being published. The great news is many of these “new” features are already available in existing tools, or being worked on.

• Enhancing PCIe Verification: How to Step Off the Map

  Article - Mar 01, 2024 by Irivinti Shiva Teja - Siemens EDA

  This article intends to propose a range of strategies that an RC might use to ‘generate’ addresses that fall outside the standard scope, along with a detailed examination of the subtle complexities involved. Initially, we will explore two relatively simple methods to accomplish this. Following that, we will analyze the limitations inherent in these methods.

• Tool Assisted Debug in Visualizer

  Article - Mar 01, 2024 by Richa Jha - Siemens EDA

  Verification is one of the primary challenges in current times when designs are huge, and corresponding testbenches are equally large. Both the design and testbench work together to fulfill the desired expectations of the designer. Everything goes well until the simulation does not work as expected. This is where Visualizer, the debug platform, plays a crucial role in figuring out where the problem lies. Visualizer requires multiple databases to provide the debug features.

• Formal Verification: An Introduction and Exploration of Challenges

  Article - Mar 01, 2024 by Yusuf Eren - ANKASYS

  Nowadays, the formal verification is getting more popular compared to the conventional simulation-based verification. The main idea behind the formal verification is to mathematically prove or disprove the correctness of a design with respect to the specification or requirement and ensure that the design behaves as intended under all possible scenarios. To achieve this, the formal verification tools are using Satisfiability Modulo Theories (SMT) solver engines.

• Maximize Returns on Your Hardware Emulation Investment with the Veloce Enterprise (ES) App

  Article - Mar 01, 2024 by Chuck Banken, Chenguang Li - Siemens EDA

  Hardware-Assisted verification (HAV) with emulation is widely regarded as crucial for successfully designing, verifying, and deploying large ASICs and even FPGAs. An emulator is a major capital investment, and customers are highly motivated to get the maximum benefit from their expenditure.

• A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP

  Resource (Recording) - Mar 01, 2024 by Lakshya Miglani, Priyanka Gharat, Gopi Srinivas Deepala - Silicon Interfaces

  This article introduces a revolutionary 64-bit native Vedic multiplier design, inspired by the Urdhva Tiryagbhyam sutra-based algorithm by Scientist Bharati Krishna Tirtha. The architecture offers superior power, timing, and area optimization, showcasing its potential for Processors, multi-cores, and DSPs computation needs. The differentiator between the current implementation and to past is the vastly enhanced native implementation of the algorithm.