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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • RISC-V Design - Webinar
      • Exploring Formal Coverage
      • Processor Customization
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar
    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings
    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - July 2023
      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us
    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
  • Home
  • About Us
  • Subject Matter Experts (SME's)

Subject Matter Experts (SME's)

Harry Foster

Harry Foster - Chief Scientist Verification

Harry Foster is Chief Scientist Verification for the Design Verification Technology Division of Siemens EDA; and is the Co-Founder and Executive Editor for the Verification Academy. In addition, Harry served as the 2021 Design Automation Conference General Chair, and is currently serving as Past Chair for DAC 2022. He holds multiple patents in verification and has co-authored six books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

Industry Data and Surveys
2022 Functional Verification Study 2020 Functional Verification Study 2018 Functional Verification Study 2016 Functional Verification Study 2014 Functional Verification Study - ASIC/IC Trends 2014 Functional Verification Study - FPGA Trends 2012 Functional Verification Study
Featured Sessions
The Three Pillars of Intent-Focused Insight Trends in Functional Verification FPGA Verification Maturity: A Quantitative Analysis First Pass Success Depends on Holistic Planning that Includes Formal Editor Insight - Handling Inconclusive Assertions Debugging Trends, Challenges, and Novel Solutions Applying Big Data Analytics to Today’s Functional Verification Challenge UVM Debug Editor Insight Conquering the New IP Economy Industry Trends in Today’s Functional Verification Landscape Verification Patterns: An Optimized Reusable Solution UVM Everywhere: Industry Drivers, Best Practices, and Solutions Fireside Chat Verification Panel Trends in Debugging: From Challenges to Solutions Industry Standards and FPGA Verification Trends Trends in Formal Verification: Not Just for Experts Anymore! From Tightly Coupled (Loosely Bolted) to Verification Convergence!
Courses
Evolving Verification Capabilities Getting Started with Formal-Based Technology Assertion-Based Verification Clock-Domain Crossing Verification Metrics in SoC Verification Evolving FPGA Verification Capabilities
Verification Patterns Libary
Absence Property Pattern Bounded Existence Property Pattern Existence Property Pattern Forbidden Sequence Property Pattern Universality Property Pattern Precedence Chain Property Pattern Precedence Property Pattern Response Chain Property Pattern Response Property Pattern
Verification Horizons
Back to the Future with Formal Property Checking What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You Quantifying FPGA Verification Effectiveness FPGA Verification Challenges and Opportunities The Verification Academy Patterns Library Does Design Size Influence First Silicon Success?
Resources
Coverage Cookbook Verification Horizons Blog Verification Patterns – Taking Reuse to the Next Level
Seminars
Assertion-Based Verification for FPGA and IC Design Design & Verification in the SoC Era

Tom Fitzpatrick

Tom Fitzpatrick - Verification Evangelist

Tom is a Strategic Verification Architect at Siemens Digital Industries Software (Siemens EDA) where he works on developing advanced verification methodologies and educating users and partners on their adoption. He has been a significant contributor to several industry standards, both in Accellera and IEEE, that have dramatically improved the functional verification landscape over the last 20 years, including Verilog 1364, SystemVerilog 1800, UVM 1800.2 and he is a founding member and current Vice-Chair of the Portable Stimulus Working Group and currently serves as the Chair of the IEEE 1800 and Accellera UVM-AMS Working Groups. He is also the 2019 recipient of the Accellera Technical Excellence Award in recognition of his many contributions over the years. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification, Portable Stimulus, and other functional verification topics and has produced some of the most popular and successful video training courses on Siemens’ Verification Academy website. He is also the editor of Siemens’ Verification Horizons newsletter, which is received quarterly by tens of thousands of subscribers. Tom is a long-time member of the Design and Verification Conference (DVCon US) Steering Committee, having served in multiple roles including Technical Program Chair and General Chair, and is a member of the Design Automation Conference (DAC) Executive Committee, serving as Special Programs Chair for 2022 and 2023. Tom holds Master’s and Bachelor’s degrees in EE/CS from MIT, is an avid golfer and a huge Boston Red Sox and New England Patriots fan, and has been married to his wife, Dee, for 26 years.

Featured Sessions
Applying Big Data to Next-Generation Coverage Analysis and Closure Verification Learns a New Language: An IEEE 1800.2 Python Implementation Optimizing Time to Bug UVM and Portable Stimulus: A Match Made in Heaven Questa inFact PSS-Infused Apps Make the Most of Your UVM Stay Ahead of the Curve: Questa Verification IP and Portable Stimulus Maximize Your UVM Productivity Portable Stimulus: Is It Revolution or Evolution? UVM 1800.2 & The New and Improved UVM Cookbook Portable Stimulus: A New Hope An Introduction to DO-254 and Advanced Verification A Fresh Look at UVM and the New UVM Cookbook Portable Stimulus is Here! (Almost) Get a Head Start on the New UVM Standard Get Ready for Portable Stimulus Off and Running with UVM Boosting Test-Creation Productivity with Portable Stimulus UVM Rapid Adoption: A Practical Subset of UVM UVM Technology Overview Navigating the Perfect Storm: New School Verification Solutions Advanced Verification Technologies in the Real World
Courses
Portable Stimulus Basics UVM Basics Advanced UVM
Resources
Verification Horizons Verification Horizons Blog UVM Cookbook Portable Stimulus Seminar On-Demand Seminars

Dave Rich

Dave Rich - Senior Verification Consultant

Dave Rich is a Verification Architect in Product & Solutions Management Ecosystem team at Siemens. He is chartered with cultivating the content of the Verification Academy and moderating its forum discussions. He is also responsible for widespread adoption of various standards and testbench methodologies. Dave brings over three decades of design and verification experience to bear on developing advanced verification methodologies. He has been actively involved in the standardization of SystemVerilog, via Accellera and now the IEEE, where he is serving as Technical Chair of the SystemVerilog IEEE 1800 Working Group. Dave was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM). That became the basis of the Universal Verification Methodology(UVM) Prior to that, Dave worked on early simulation and synthesis technologies at Cadence and Synopsys getting people to adopt Verilog.

Course
SystemVerilog OOP for UVM Verification
Resources
Verification Horizons Blog Introspection Into SystemVerilog Without Turning It Inside Out Of Camels and Committees - Standards Should Enable Innovation, Not Strangle It
Featured Sessions
The Life of a SystemVerilog Variable Verilog Basics for SystemVerilog Constrained Random Verification SystemVerilog OOP Basics used in UVM Verification Debug Data API Update
Papers and Articles
Standards Participation at Siemens EDA Introspection Into SystemVerilog Without Turning It Inside Out Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI

Chris Spear

Chris Spear - Functional Verification Principal Instructor

Chris brings over twenty five years of EDA expertise to Siemens EDA customers and is currently a Functional Verification Principal Instructor with Siemens EDA Learning Services. Holding a degree in electrical engineering from Cornell University, Chris has developed deep roots in the EDA industry, including as a Principal Application Consultant with Synopsys. Chris is also an industry author, writing the 2012 best-selling “SystemVerilog for Verification” and developing the IEEE standard for random seeding and File I/O PLI package that is part of SystemVerilog. Having taught thousands of engineers around the world, Chris is driven by a passion for learning new techniques and then helping others learn best practices for hardware verification. Outside of work, you may see Chris bicycling over 10,000-foot mountain passes.

Featured Sessions
Runtime checks with the $cast() method Verification Class Categories SystemVerilog Class Variables and Objects Getting Started with Questa Memory Verification IP UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know Get Your Bits Together: SystemVerilog Structures and Packages Taking SystemVerilog Arrays to the Next Dimension SystemVerilog Class Variables and Objects Stimulating Simulating: UVM Transactions  Stimulating Simulating 2: UVM Sequences
Verification Horizons Blog
Why are UVM transactions built with uvm_sequence_item? What Does Importing a SystemVerilog Package Mean? Get Your Bits Together SystemVerilog Multidimensional Arrays Getting Organized with SystemVerilog Arrays UVM Configuration DB Guidelines SystemVerilog Static Methods SystemVerilog Classes with Static Properties SystemVerilog Parameterized Classes Tips for new UVM users
Instructor Led & On-Demand Training
Functional Verification Training Library

Jacob Wiltgen

Jacob Wiltgen - Functional Safety Solutions Manager

Jacob Wiltgen is the Functional Safety Solutions Manager for Siemens EDA and is responsible for defining and aligning functional safety technologies across the portfolio of IC Verification Solutions. He holds a Bachelor of Science degree in Electrical and Computer Engineering from the University of Colorado Boulder. Prior to Mentor, Jacob has held various design, verification, and leadership roles performing IC and SOC development at Xilinx, Micron, and Broadcom.

Course
Introduction to ISO 26262
Resources
Achieving Functional Safety for Autonomous Vehicle SoC Designs
Featured Sessions
Optimizing a Fault Campaign for Complex Mixed-Signal Devices Mentor + Siemens Provides Solutions and Expertise to Achieve Rapid Safety Compliance

Chris Giles

Chris Giles - Design Solutions Product Manager

Chris Giles is the Head of Product Management for Static and Formal Solutions. Chris comes to Siemens EDA from the user community, with decades of experience in IP and ASIC/SoC/FPGA R&D and management, with products deployed in consumer, military, compute and storage markets and at companies such as Hewlett Packard Enterprise, Honeywell, Seagate, Micron and LSI Logic. The author of 18 patents in areas such as hardware virtualization, security, processor architecture, synchronization schemes, and hardware prototyping, Chris received an MSEE from Stanford University in California and a BSEE from Rice University in Texas.

Verification Horizons Blog
Leave the House With a Clean Design
Featured Sessions
Productive Development: Leveraging Early Design Insight to Accelerate Learning Curves and Achieve Program Goals Efficiently Improving Initial RTL Quality When Are You Done Running CDC? Confronting Inevitability: Finding Clock and Reset Issues Before They Find You Mind the Gap(s): Closing and Creating Gaps Between Design and Verification

Gordon Allan

Gordon Allan -

Gordon Allan is the Questa Verification IP Product Manager at Siemens EDA. Gordon was one of the architects and developers of Accellera UVM, and was responsible for the UVM/OVM Methodology Cookbooks published on the Verification Academy website and appreciated by over 65,000 engineers worldwide, as well as several conference papers on Verification topics at DVCon and elsewhere. Prior to joining the EDA industry in 2010 he gained over 18 years of SoC Design and Verification experience in lead engineer and senior consultant roles, working with many of the top semiconductor companies, fabless startups, system houses and EDA companies worldwide and giving him firsthand experience of customers’ challenges from spec to tapeout. Gordon is based in Silicon Valley.

Featured Sessions
New Leader in Verification IP, Delivering First Silicon Success for Your Next SoC or 3DIC Verification of HPC Protocols and Memories Preparing for PCIe 6.0 - Part II - Verification of PCIe IP VIP Solutions for Protocol and Memory Verification Productivity in the Questa Simulation Flow Productive Low Power Debug Across All Engines and Flows Breaking the Speed Limits on SoC Verification SoC Verification with the Questa® Flow System Level Debug & Analysis Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs Improving UVM Testbench Debug Productivity and Visibility Evolution of Debug
Resources
UVM Cookbook Verification Horizons Blog The Evolution of Triage - Real-time Improvements in Debug Productivity The Big Brain Theory: Visualizing SoC Design & Verification Data Tried/Tested speedups for SW-driven SoC Simulation

Darron May

Darron May - Product Marketing Manager

Darron May has over 30 years of experience in the electronics industry including board, FPGA, and chip design & verification, pre and post sales support, applications, consulting and technical marketing. As a Product Manager in the Design Verification Technology Division of Siemens EDA, Mr. May has most recently been focused on architecting Verification Management solutions based on customer requirements and driving the deployment of the tools worldwide. Prior to Mentor Graphics, Mr. May has held positions in the engineering and applications management in the Datacoms and EDA industries, for Racal Datacom, Racal Research, Model Technology Inc., and through distribution including Synplicity, Summit Design, TSSI, InterHDL, and Simucad. Mr. May holds an HND in Electronic Engineering from Basingstoke college of technology.

Featured Sessions
Questa Verification IQ: Boost verification predictability and efficiency with Big Data Collaborative Verification Management & Coverage Analysis Streamlining Plan & Requirements Driven Verification Jenkins Installation & Setup Jenkins Project Configuration Jenkins VRM Integration Demo New School Regression Control
Verification Horizons
Mentor Has Accellera's Latest Standard Covered Automation Management: Are You Living a Scripted Life? Process Management: Are You Driving in the Dark with Faulty Headlights? Data Management: Is There Such a Thing as an Optimized Unified Coverage Database?
Technical Papers
Are You Really Confident That You Are Getting the Very Best From Your Verification Resources? Improving Verification Predictability and Efficiency Using Big Data

Kurt Takara

Kurt Takara -  Senior Product Engineer

Kurt Takara is a Senior Product Engineer for Questa CDC+RDC at Siemens EDA, and has over 20 years of experience in engineering design and verification, technical marketing and engineering services. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as 0-In Design Automation, Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.

Featured Sessions
Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC CDC Philosophy: The existential questions of constraints, waivers, and truth A Methodology for Comprehensive CDC+RDC Analysis Advance your Designs with Advances in CDC and RDC Mind the Gap(s): Closing and Creating Gaps Between Design and Verification Why Reset Domain Crossing Verification is an Emerging Requirement Clock-Domain Crossing Analyses and Verification No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff! What Is CDC Protocol Verification, Prevent Bugs in Your Silicon How to Keep UPF from Ruining Your CDC Analysis Next-Generation Power Aware CDC Verification – What Have We Learned? Questa® CDC Verification Demo
Course
Power Aware CDC Verification
Featured Resources
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic Reset Verification in SoC Designs Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling Artifacts

Mark Eslinger

Mark Eslinger - PRODUCT ENGINEER

Mark Eslinger is a Product Engineer in the IC Verification Systems division of Siemens EDA where he specializes in assertion-based methods and formal verification. Mark has over 25 years of experience in design and verification, applications engineering, and technical marketing.

Featured Sessions
Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy Formal 101 – Setting Up & Optimizing Constraints Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal Deadlock Verification For Dummies Should I Kill My Formal Run? Part 2: Avoid Trouble and Set Yourself Up For Success How to Unearth Deep Bugs Faster and Cheaper Using Formal Bug Hunting Techniques Formal Verification: Automation and Tips for Success Setup a Formal Testbench Use Formal to Check Logic Faults Close the Verification Loop Interactive Formal Debug and Design Exploration New Coverage Closure Techniques New School Connectivity Checking New School Coverage Closure Questa® Formal Verification Demo
Courses
Formal Coverage Formal-Based Technology: Automatic Formal Solutions Formal Assertion-Based Verification
Resources
Formal Bug Hunting with “River Fishing” Techniques

Moses Satyasekaran

Moses Satyasekaran - Product Manager

Moses Satyasekaran, is a Product Manager at Siemens EDA for the Questa Simulator product. Moses has more than 11 years of experience in the FPGA synthesis and verification technologies. Moses is a graduate of University of Colorado Boulder.

Featured Session
Enterprise Debug for Simulation

Mark Olen

Mark Olen - Product Marketing Manager

Mark manages the product marketing team at Siemens EDA’s Design Verification Technology Division. He and his team are responsible for product management and marketing of Siemens EDAs’ Enterprise Verification Platform (EVP), including simulation, formal verification, verification IP, portable stimulus generation, unified verification management, and common debug technology. Mark has spent over 30 years in sales, marketing, and management positions in the semiconductor design, manufacturing, and test industries. He graduated from the Massachusetts Institute of Technology.

Verification Horizons
Is Intelligent Testbench Automation For You? Software-Driven Testing of AXI Bus in a Dual Core ARM® System
Featured Sessions
Data Mining for SoC Level Performance Verification IP & Memory Models Improve Productivity & Reduce Risk Verification IP and Memory Models Accelerating Time to Coverage Closure

Ann Keffer

Ann Keffer - Functional Safety Verification Product Marketing Manager

Ann Keffer is the worldwide Product Marketing Manager for functional safety verification at Siemens EDA. Ann started her career as a software developer for Hewlett Packard writing operating system code. After a few years in R&D, she moved into application engineering, then product marketing and finally marketing management. She has since led worldwide marketing and product management for companies in the automation, robotics and automotive functional safety verification industries.

Featured Sessions
Achieving High Defect Coverage for Safety Critical and High Reliability Designs Validation of Complex Safety Architectures

Rich Edelman

Rich Edelman - Product Engineer

Rich Edelman is a Product Engineer at Siemens EDA for the Visualizer Debug Environment. He is a verification technologist helping customers adopt successful techniques for UVM and class based testbenches. Rich previous work includes register verification, SystemVerilog DPI development and transaction recording interfaces for Questa. Rich graduated from Washington University in St. Louis with a bachelor's degree in Computer Science, a bachelor's degree in electrical engineering and a master's degree in computer science.

Featured Sessions
Accelerate Development Using Advanced Debugging Approaches Making Your DPI-C Interface A Fast River Of Data I Didn’t Know Visualizer Could Do That Introduction to Visualizer for the VHDL Users Introduction to Visualizer for the Verilog Users Better UVM Debug with Visualizer Context-Aware Debug for Complex Heterogeneous Environments Better UVM Debug with Visualizer Debugging Your Design in a Heterogeneous Environment UVM Debug? Beyond Logfiles Goldilocks and System Performance Modeling Are You Smarter Than Your Testbench? With a Little Work You Can Be Verification and Debug: Old School Meets New School
Accelerate Development Using Advanced Debugging Approaches
Technical Papers
Transaction Recording Anywhere Anytime UVM IEEE Shiny Object DPI Redux. Functionality. Speed. Optimization. No RTL Yet? No Problem - UVM Testing a SystemVerilog Fabric Model UVM Sans UVM - An approach to automating UVM testbench writing Beyond UVM Registers - Better, Faster, Smarter Monitors, Monitors Everywhere – Who Is Monitoring the Monitors Are You Smarter Than Your Testbench? With a Little Work You Can Be
Verification Horizons
Getting to Know Visualizer, Part II Getting to Know Visualizer Fun with UVM Sequences - Coding and Debugging No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model
Resources
Verification Horizons Blog

Graeme Jessiman

Graeme Jessiman - Applications Engineering Team Leader

Graeme Jessiman is an Applications Engineering Team Leader at Siemens EDA based in Scotland. For over 25 years he has supported Siemens simulation and static/formal tools for European customers spanning many different industry segments. One key area has been helping VHDL customer adopt advanced verification methodologies such as UVMF. Graeme hold as BSc (Hons) in Electrical and Electronic Engineering from the Robert Gordon University in Aberdeen, is a Chartered Engineer and a member of the IET.

Featured Sessions
Installing Python On Windows for use with UVMF Generating UVMF code on Windows Simulating UVMF code on Windows

Nick Galvan

Nick Galvan - Applications Engineer

Nick Galvan is Applications Engineer within the Design Verification Technologies group. He graduated from Colorado State University and has continued to call Colorado home. He has over 9 years of experience designing and verifying ASICs and FPGAs. Much of Nick’s career was at SEAKR Engineering where he worked on verifying ASICs and FPGAs for satellite communications. Nick also worked as a verification engineer at Lockheed Martin Space Systems, verifying complex systems for special programs and acting as the lead verification engineer. In addition, Nick has worked at Medtronic verifying FPGAs for medical devices and at Intel for the Clocking and Security group.

Featured Sessions
Register adapters, predictors, and tests in UVMF

Jason Polychronopoulos

Jason Polychronopoulos - Verification Technologiest

Jason Polychronopoulos is a Verification Technologist at Siemens EDA. He has over 14 years of experience in functional verification, verification tools, methodologies and design of verification IP. Mr. Polychronopoulos holds a Masters in Electronic Engineering from The University of Manchester.

Silicon Valley Design and Verification IP Forum
Leveraging the latest DDR & Flash Memory Models Creating a Thorough Verification Environment in Less Than Two Days
Featured Sessions
Interactive Debug Techniques for UVM, SystemVerilog & RTL using Visualizer Productive Verification with VIP, a UVM Framework and Configuration GUI Leveraging Verification IP (VIP) for Fast & Efficient Verification EZ Design and Verification of ARM® AMBA® Based Designs New School Thinking for Fast & Efficient Verification Using EZ-VIP

Adam Erickson

Adam Erickson - Verification Methodologist

Adam Erickson is a Verification Methodologist at Siemens EDA, where he’s served as a principal developer of the OVM, UVM, and UVM Connect. Since earning his Masters in Engineering Sciences at Dartmouth College, Adam has collected 22 years experience in design, verification, and implementation of integrated circuits for companies large and small. He has committed the last 16 of those years developing EDA software and methodological solutions for increasing productivity and reuse in verification. He has authored articles for Verification Horizons and published several conference papers, including Best Paper on a cost-benefit analysis of UVM macros at DVCon 2010. When he’s not improving existing solutions or developing ideas for new ones, Adam can often be found teaching their virtues to others. Adam is currently the primary technical representative for Siemens EDA on the Accellera VIP-TSC, the committee responsible for UVM standardization.

Course
UVM Connect
Verification Horizons
Introducing UVM Connect Are OVM & UVM Macros Evil? A Cost-Benefit Analysis
Resources
UVM Connect Cookbook UVM Connect Reference
Technical Paper
Transaction-Level Friending: An Open-Source, Standards-Based Library for Connecting TLM Models in SystemC and SystemVerilog

Joe Hupcey

Joe Hupcey - Verification Product Technologist

oe Hupcey III is a part of the Siemens EDA Product Management team for Design & Verification Technologies; based in Siemens’ office in Silicon Valley, CA. He is responsible for the Formal product line of automated applications and advanced property checking. Prior to joining Siemens, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, Joe worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.

Featured Sessions
Formal and the Next Normal From Zero to Hero: How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification ‘The Dog Ate my RTL’ Doesn’t Work Anymore Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal How Do I Verify My Rescue Drone's RTL Select and Run Automated Formal Apps Enterprise Debug for Formal Orange is the New Black, Reset Verification is the New CDC How Secure is Your System? Introduction to Automated Formal Apps Introduction to Formal Assertion-Based Verification Formal Verification: Automation and Tips for Success
Formal 101
Fast, Scalable Formal Verification Made Easy Exhaustive Scoreboarding and Data Integrity Verification Made Easy Setting Up & Optimizing Constraints Basic Abstraction Techniques
Resources
Verification Horizons Blog Advanced Validation & Verification Techniques for Complex Low Power SoCs Back to Basics: Doing Formal “The Right Way” Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Verification Horizons
How Formal Techniques Can Keep Hackers from Driving You into a Ditch

Sven Beyer

Sven Beyer - Program Manager, Formal Processor Verification

Sven Beyer is the Program Manager for Formal Processor Verification at Siemens EDA (Siemens Digital Industries Software). Sven has close to twenty years of experience in formal verification, with a specific focus on industrial processor verification. Prior to Siemens EDA, he was with OneSpin Solutions since its inception, filling various roles involving methodology, application, and product management. He has been instrumental to the development of many formal verification IPs and apps and holds several patents, including one for processor verification.

Sven has led numerous formal processor verification projects, such as the work on Infineon's TriCore processor. His most recent work involves the automation of the verification of RISC-V based architectures. Sven holds a Dr.-Ing. (equivalent to a PhD) in computer science from Saarland University, Germany, where his PhD thesis was focused on the formal verification of an out-of-order processor core.

Rich Powlowsky

Rich Powlowsky - Strategic Accounts - Defense

Rich Powlowsky is responsible for the Defense business for Siemens EDA. He has handled Strategic Accounts at Mentor/Siemens for 4.5 yrs, previously at Cadence for 18 years. Rich graduated from Univ. of New Hampshire is BS Computer Engineering in 1984. His first 5 years were in Systems design for RCA Defense Systems, now Lockheed Martin.

Featured Session
Siemens and the US Government - Mitigating Microelectronics Development Challenges

David Landoll

David Landoll - Solutions Architect

David is a Solutions Architect at Siemens OneSpin where he works to develop and deploy formal tools and methodologies. In addition, David focuses on safety, security, and trust related industries, including department of defense, automotive and avionics. David has extensive experience in DO-254 and ISO-26262 safety standards, and has presented at numerous conferences and events, and is a member of the North America DO-254 Users Group. David has over 20 years of formal verification experience, and almost 30 years of design and verification experience, and has directly managed and contributed to large projects including an ADAS self driving car system, and large safety critical avionics SOCs. He has BSEE from the University of Arizona, and MBA from Santa Clara University.

Featured Session
From Zero to Hero: How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification

Kevin Campbell

Kevin Campbell - Technical Product Manager

Kevin Campbell is a Technical Product Manager at Siemens EDA and is responsible for Questa Design Solutions products. He holds a Bachelor of Science Degree in Electrical and Computer Engineering from New Mexico State University. Prior to Siemens EDA, Kevin has held a variety of positions in RTL design and verification, as well as leadership roles on teams at Seagate, Micron and Intel.

Feature Session
Continuous Integration (CI) driving efficient program execution Questa Lint vs Formal AutoCheck

Gabriel Chidolue

Gabriel Chidolue - Product Engineer

Gabriel Chidolue is a Product Engineer in the IC Verification Solutions group within Siemens EDA, a part of Siemens DI SW. He has over 20 years’ experience in Digital design and verification. His current focus area is on functional verification of UPF based Power Managed designs. His main responsibilities include creation and deployment of verification methodologies and solutions in close collaboration with R & D, Siemens EDA Customers, Partners and active participation and contribution within IEEE P1801 WG.

Mr. Chidolue holds a B.Eng in Electrical Engineering from University of Nigeria, Nigeria and an M Sc in Concurrent Engineering for Electronic Product Design from Bournemouth University, United Kingdom.

Featured Session
Leveraging Advancements in UPF 3.1 for Effective Design and Verification

Russell Klein

Russell Klein - Program Director

Russell Klein is a Program Director at Siemens EDA’s High-Level Synthesis Division focused on processor platforms. He is currently working on algorithm acceleration through the offloading of complex algorithms running as software on embedded CPUs into hardware accelerators using High-Level Synthesis. He has been with Mentor for over 25 years, holding a variety of engineering, marketing and management positions, primarily focused on the boundary between hardware and software. He holds six patents in the area of hardware/software verification and optimization. Prior to joining Mentor he worked for Synopsys, Logic Modeling, and Fairchild Semiconductor.

Featured Sessions
From Model to Implementation with High-Level Synthesis System Level Debug with Emulation Various Methods for Debugging Software in Emulation Full SoC Emulation from Device Drivers to Peripheral Interfaces
Verification Horizons
Optimizing Emulator Utilization

Felipe Schneider

Felipe Schneider - Applications Engineering Manager

Felipe Schneider is Applications Engineering Manager for team supporting Siemens EDA's IP Validation solutions worldwide. Felipe has contributed in the EDA industry for more than 17 years with mixed R&D and Field Engineering roles. His experience (software engineering and silicon design) spans multiple design disciplines: from automatic layout generation and characterization to logic & physical synthesis, transistor-level STA and finally, how to put it everything together without hurting the tapeout schedule of design team. The latter ultimately landed him at Fractal Technologies, acquired by Siemens in 2021. Felipe holds a B.Eng. in Computer Engineering and a M.Sc. in Computer Science, Microelectronics from Federal University of Rio Grande do Sul, Brazil.

Featured Session
Trust but Verify Your IP with Solido Crosscheck

Bob Oden

Bob Oden - UVM Specialist

Bob Oden is a UVM Field Specialist at Siemens EDA, where he helps customers across North America adopt UVM and advanced verification methodologies. During his tenure at Mentor he has created the UVM Framework, which is used to establish a verification library that supports horizontal, vertical, and platform reuse. Bob has over 25 years of experience using eRM, AVM, OVM, and UVM. He holds three U.S. patents and a BSEE from California State University, Chico. Bob is also an instructor at NCSU where he teaches ECE745, “ASIC Verification”, and ECE748, “Advanced Verification with UVM”.

Course
UVM Framework - One Bite at a Time
Featured Session
Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
Verification Patterns Library
Component Configuration Pattern Environment Layering Pattern
Technical Papers
Slaying the UVM Reuse Dragon A Simplified and Reusable UVM Config DB Methodology for Environment Developers and Test

Byran Ramirez

Byran Ramirez - Product Manager

Bryan Ramirez manages the Strategic Marketing team at Siemens EDA focused on incubating and bringing to market new solutions and driving business across key market verticals. His main responsibility has been driving the IC functional safety strategy for ISO 26262 and the automotive market. Bryan joined Mentor in February 2015. He brings 15+ years of IP and SOC experience leading and managing design and verification teams at Xilinx, Seagate and Paneve.

Featured Session
End-to-end Functional Safety for ISO 26262 Staying Competitive with Modern FPGA Verification Staying Competitive with Advanced FPGA Verification

Chris Crile

Chris Crile - Senior Application Engineer

Chris Crile is a Senior Application Engineer at Siemens EDA and is responsible for Functional Verification products. He holds a Bachelor of Science Degree in Electrical Engineering from the University of Iowa. Prior to Siemens EDA, Chris held positions in RTL design and verification at Nokia and Rockwell Collins.

Featured Session
Introduction to SystemVerilog Assertions

Mathew Yee

Mathew Yee - Questa Design Solutions Applications Consultant

Mathew Yee is a lead Applications Consultant for Questa Design Solutions at Siemens EDA and has over 30 years of experience in engineering design, verification, and applications. Yee has held engineering and consulting services roles in electronics and EDA companies such as Amdahl, Applied Signal Technology, KC Technology, InnoLogic Systems, Synopsys, Axiom Design Automation, and SpringSoft. He holds a BSEE from UC Santa Barbara.

Featured Session
Introduction to Questa Lint and CDC for Designers

Buu Huynh

Buu Huynh - Sr. Product Engineer

Buu Huynh is a Sr. Product Engineer for Siemens EDA, Questa Design Solutions Team. He has over 18 years of experience as an FPGA and mixed-signal IC design engineer in the Mil-Aero and Telecom/Datacom industries.

Featured Session
Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

Vedant Garg

Vedant Garg - Functional Safety Solution Architect

Vedant Garg is the Functional Safety Solution Architect for Siemens EDA. He is responsible for defining the core safety analysis & FMEDA solution. He holds a master’s degree in computer engineering from University of Massachusetts, Lowell. Prior to Siemens EDA, Vedant was part of core IC verification RD team at Cadence.

Featured Sessions
Union of SoC Design & Functional Safety Flow Validation of Complex Safety Architectures

Athira Panicker

Athira Panicker - Product Engineer

Athira Panicker is a Product Engineer for Coverage and Verification IQ at Siemens EDA. Ms. Panicker has experience in functional verification, verification tools, and methodologies. Ms. Panicker holds a Masters in Electrical and Computer Engineering from Portland State University.

Featured Session
Visualizer Coverage: Debug and Visualize All Your Coverage

Jonathan Craft

Jonathan Craft -

Jonathan Craft is an HLS Technologist at Siemens EDA focused on development of High Level Verification (HLV) tools & methodologies. He holds a Bachelor of Science degree in Electrical Engineering from the University of Wyoming. Prior to working for Siemens, Jon held various design and verification roles performing IC and SoC development at various companies in the Denver, Colorado area.

Featured Course
UVM Framework - One Bite at a Time
Featured Sessions
UVMF build/compile/run script introduction Questa Productivity Features

Shubhankar Deshmukh

Shubhankar Deshmukh - Applications Engineer

Shubhankar is an Applications Engineer for Functional Verification at Siemens EDA, with deep technical expertise in Ethernet QVIP. He holds a graduate degree in Computer Engineering from North Carolina State University. In his EDA industry experience, Shubhankar has helped a lot of our customers to successfully adopt QVIP as a primary solution for their verification needs.

Featured Session
Ethernet Questa VIP - Boost Productivity & Faster Sign-Offs

Kamlesh Mulchandani

Kamlesh Mulchandani - Application Engineering Consultant

Kamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. He drives Questa® VIP with primary focus on Memory. He brings over 7 years of Memory Subsystem Verification experience. Prior to that he was an Assistant corporate trainer for UVM & SV where he trained Engineers at companies like Qualcomm, Broadcom, Cypress Semiconductors to name a few.

Featured Session
Comprehensive Memory Modeling - DDR Questa® Verification IP
Verification Horizons
Verifying a DDR5 Memory Subsystem

Charles Battikha

Charles Battikha - Solutions Architect

Charles Battikha is a Solution Architect for Siemens EDA’s Consulting Group specializing in Functional Verification and Functional Safety. Charles has been in the industry, focused on functional verification for over 30 years, half of them as a consultant providing solutions to such markets as automotive, nuclear, aeronautics, medical, and military. Charles started with Mentor in 2012. Prior to Mentor, Charles ran the consulting organization at LSI Logic.

Featured Resources
ISO 26262 & Fault Analysis to Fault Campaigns - Parts 1 & 2 Requirement Tracing in the ISO 26262 World - Part 4 Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task

Doug Smith

Doug Smith - Verification Engineer and Instructor

Doug Smith is a verification engineer and instructor for Doulos with expertise in UVM and formal technologies. He has been using formal technology for several decades, performing formal verification on many kinds of designs and formal applications. Likewise, he has provided formal consulting and application support at both Siemens EDA and Jasper DA. At Doulos, he delivers training in formal technology, hardware description languages, and verification methodologies.

Featured Sessions
What is Formal, Anyway? How Formal Reduces Fault Analysis for ISO 26262 Formal Verification Tips & Tricks for Fun & Profit
Technical Paper
It’s Not My Fault! How to Run a Better Fault Campaign Using Formal Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task

Tomasz Piekarz

Tomasz Piekarz - Product Engineer

Tomasz Piekarz is a Product Engineer for SoC Verification and Embedded SW Debug at Siemens EDA. He has over 20 years of experience in functional verification, verification tools, methodologies and design of SoC. Mr. Piekarz holds a Masters in Electronic Engineering from The Silesian Technical University in Gliwice (Poland).

Featured Session
Embedded Software Debug Using Codelink and Visualizer

Mark Peryer

Mark Peryer - Verification Methodologist

Mark Peryer is a Verification Methodologist within the Design Verification and Technology division at Siemens EDA and is responsible for developing and deploying verification methodologies and solutions. He developed his first verification environment for a graphics processor in the mid-eighties and although the languages and the techniques have changed, he has continued to work on hairy verification problems ever since. Mark is the author of many conference papers, articles and training classes and holds an honors degree in Electronic Engineering from Southampton University.

Verification Horizons
Celebrating 10 Years of the UVM Memories Are Made Like This Caching in on Analysis On the Fly Reset Three Steps to Unified SoC Design and Verification Online UVM/OVM Methodology Cookbook: Registers/Overview
Verification Patterns Library
Layering Sequence Pattern
Industry Article
Accurate Memory Models for All
Resources
UVM Cookbook OVM Cookbook
Technical Paper
Total Recall - What to Look for in a Memory Model Library Seven Separate Sequence Styles Speed Stimulus Scenarios Traffic Profiling and Performance Instrumentation For On-Chip Interconnects

Atul Sharma

Atul Sharma - Lead Product Engineer

Atul Sharma is the Lead Product Engineer for Questa Static Products at Siemens EDA and primarily responsible for CDC, RDC, SignOff CDC and Lint products. He holds a Bachelor of Engineer degree in Electronics and Communication Engineering from Engineering College Ajmer, Rajasthan. Started his career with Design and Verification Engineer and later moved to EDA domain.

With 15 years of total experience, he has spent over a decade in customer facing role to solve Static Verification issues (CDC, RDC, Lint, DFT, Power Estimation/Reduction & Power Verification) and to create customer methodologies, use models for multiple EDA products.

Featured Sessions
Questa CDC/RDC Assist: Applying AI/ML to accelerate closure Questa® Reset Domain Crossing (RDC) Demo A Methodology for Comprehensive CDC Analysis RDC Overview & Questa RDC Methodology

Pradeep Salla

Pradeep Salla - Functional Verification Technical Manager

Pradeep Salla manages the Verification team at Siemens EDA India. He is responsible for driving and supporting the Verification technology team and also develop markets for Siemens EDA in India. Prior to Siemens EDA, Pradeep has worked in various organizations such as Renesas Electronics, Nokia & MindTree and has a total experience of about 13 years in Functional Verification. He received his Master’s in Electrical Engineering from North Carolina State University and B.E from Bangalore University. His area of expertise include architecting reusable testbenches at IP, Subsystem and SoC level, Power Aware verification, Design for Software Debug among others.

Verification Horizons
Verification Horizons Blog QVM: Enabling Organized, Predictable, and Faster Verification Closure
Verification Patterns Library
Strategy Pattern Façade Pattern Walking Pattern
Technical Papers
Verification Patterns - Taking Reuse to the Next Level
Committees
DVCon India Steering Committee

Nicolae Tusinschi

Nicolae Tusinschi - Formal Verification Solutions Product Manager

Nicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental, Nicolae joined OneSpin, where he worked in QA, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics, leveraging coverage results in the verification process, formal verification of RISC-V cores.

Featured Sessions
Exploring the Multi-faceted Landscape of Formal Coverage Efficient Interconnect Formal Verification for Complex, Large-scale Designs

Sumit Vishwakarma

Sumit Vishwakarma - AMS Product Marketing

Sumit Vishwakarma has over 15 years of experience in the EDA industry including 10 years in AMS and 5 years in digital verification. At Siemens EDA, Sumit is responsible for product management and marketing functions across Siemens EDA’s AMS verification product portfolio driving circuit simulation, mixed-signal, and library characterization platform. Over the years, Sumit has held various roles ranging from design engineer, application engineer and verification specialist at Intel, Springsoft and Synopsys. Before joining Siemens EDA, Sumit was responsible to drive the sales and development of Analog/Mixed-Signal simulators and verification and debug platforms at Synopsys. He has published papers in IEEE, DesingCon, DAC, SNUG, U2U and multiple tech articles and blogs on mixed signal verification methodologies. Sumit has a MS in Electrical engineering from Arizona State and Management Science & Engineering PD from Stanford. He is a vivid digital artist and love teaching art to kids.

Featured Sessions
A Novel Variation-Aware MSV Methodology to Achieve High-Sigma Variation Coverage Methodology to Debug Real Number Model (RNM) Boundary Scenarios
Verification Horizons
The Democratization of Digital Methodologies for AMS Verification "Hug the Debug" – Before It’s Too Late

Steve Geisler

Steve Geisler - Senior Staff Engineer and UI Manager

Steve is a software developer and also oversees the development of user interfaces for Questa Formal and CDC product lines at Siemens EDA. Steve has over 30 years of experience creating EDA tools in areas such as logic synthesis, wire harness design and equivalence checking. He earned his BSCS from University of Pittsburgh. Steve is also the tournament director and head judge for the annual FIRST FLL robotics tournament sponsored by Siemens EDA.

Hirak Roy

Hirak Roy - Engineering Manager

Hirak completed his Masters and Bachelors (M.Tech & B.Tech) in Computer Science and Engineering from Indian Institute of Kharagpur in 2006. Hirak began his career with the Precision Synthesis team and is now leading the Questa Formal Verification R&D team at Siemens EDA's Noida Development Center.

Kaushal Pathak

Kaushal Pathak - Staff Engineer

Kaushal is a Staff Engineer in the DVT Formal Verification Group for Siemens EDA. He is responsible for developing GUI for Questa Formal. Kaushal earned his B.Tech in Computer science from Karnataka University in India in 1996. He has been involved in GUI development for more than 20 years and has previously worked for Cadence, Synopsys and Montrey Design Systems.

Progyna Khondkar

Progyna Khondkar - Low Power Design & Verification Expert

Progyna Khondkar, is a low power design & verification expert and senior verification engineer at Siemens EDA in the Design Verification Technology Division (DVT). He holds two patents and authored; Low Power Design and Power Aware Verification, that will be published from Springer in September 2017. He also has numerous publications in power aware verification. He has strong focus on electronics, computer and information science education, research and teaching experiences in top level universities in Asia. He has been working for hardware/software design, development, integration, test and verification in the world class ASIC & Electronic Design Automation (EDA) companies for last 15 years. He holds a Ph.D Computer Science and a senior member of IEEE. He also serves as a member of editorial board and reviewer of Journal of Information, IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, IEEE Transactions on Computers and Journal of VLSI Design and Verification (JVLSIDV).

Verification Horizons
Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs Part I: Power Aware Static Verification—From Power Intent to Microarchitectural Checks of Low-Power Designs PA GLS: The Power Aware Gate-level Simulation Understanding the UPF Power Domain and Domain Boundary
Technical Papers
UPF Information Model: The Future of Low-Power Verification Today Low Power Coverage: The Missing Piece in Dynamic Simulation Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF The Fundamental Power States for UPF Modeling and Power Aware Verification
Featured Session
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

Matthew Ballance

Matthew Ballance - Verification Technologist

Matthew Ballance is a Product Engineer and Portable Stimulus Technologist at Siemens EDA, working with the inFact Portable Stimulus product and the Accellera Portable Stimulus Working Group. Over the past 20 years in the EDA industry, he has worked in product development, marketing, and management roles in the areas of hardware/software co-verification, transaction-level modeling, IP encapsulation and reuse, and Portable Test and Stimulus.

Featured Sessions
Find Bugs Earlier with Strategy-Guided Stimulus Portable Stimulus from IP to SoC - Achieve More Verification Testbench Automation - Testbench Automating Reusable, Retargetable Scenario-Level Tests with Portable Stimulus Automating Scenario-Level UVM Tests with Portable Stimulus New School Stimulus Generation Techniques Old School vs New School Stimulus Generation Techniques Portable Stimulus from IP to SoC - Achieve More Verification PSS Usage Examples
Verification Horizons
Designing A Portable Stimulus Reuse Strategy Exercising State Machines with Command Sequences Creating Tests the PSS Way in SystemVerilog Building a Better Virtual Sequence with Portable Stimulus Creating SoC Integration Tests with Portable Stimulus and UVM Register Models Make Your Constraints More Dynamic with Portable Stimulus Getting Generic with Test Intent: Separating Test Intent from Design Details with Portable Stimulus Smoothing the Path to Software-Driven Verification with Portable Stimulus Portable VHDL Testbench Automation with Intelligent Testbench Automation Targeting Internal-State Scenarios in an Uncertain World Power Up Hardware/Software Verification Productivity
Resources
Results Checking Strategies with Portable Stimulus Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy Making Legacy Portable with the Portable Stimulus Specification Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse Jump-Start Software-Driven Hardware Verification with a Verification Framework Tackling Random Blind Spots with Strategy-Driven Stimulus Generation Boost Verification Results by Bridging the Hardware/Software Testbench Gap

Ping Yeung

Ping Yeung - Principal Engineer

Ping Yeung, Ph.D. is the Principal Engineer in Siemens EDA. He has over 20 years application, marketing, and product development experience in the EDA industry, including positions at 0-In, Synopsys, and Mentor Graphics. He holds 7 patents in the CDC and formal verification areas.

Featured Sessions
Trouble: Three CDC Glitches That Only a Netlist Will See Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunting Preventing Glitch Nightmares on CDC Paths: The Three Witches Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt Clock-Domain Crossing with HDM - Enhanced Accuracy and Seamless Visibility at SOC Level

Neil Johnson

Neil Johnson - Senior Product Engineering Manager

Neil Johnson is a long time verification engineer with a history in product development as both a full-timer and a consultant, now working with Siemens EDA as a Senior Product Engineering Manager responsible for QuestaSim.

Featured Sessions
Practical Flows for Continuous Integration: Making The Most of Your EDA Tools I'm Excited About Formal... My Journey From Skeptic To Believer Building An Integrated Verification Flow Add Unit Testing To Your Verification Tool Belt Back to the Stone Ages for Advanced Verification An Agile Evolution in SoC Verification
Course
Introduction to Unit Testing with SVUnit
Verification Horizons
First Time Unit Testing Experience Report with SVUnit Unit Testing Your Way to a Reliable Testbench Expediting Simulation Turn-around Time with Incremental Build Flow
Blogs
Webinar Preview: Practical Flows for Continuous Integration Performance Profiling How-To (Make My Testbench Faster) Simulation Performance Profiling Like a Pro Qrun-ing Optimized Build Flows in Questasim Expediting Simulation Turn-around Time with Incremental Build Flows Formal Flows From a Simulation Point-of-View Formal Level 6: Property-Driven Development Your First Step Into Formal Property Checking I’m Excited About Formal Property Checking! My Journey From Skeptic to Believer SystemVerilog Race Condition Challenge Methodology by Example – 6 Approaches to Verification The Ideal Verification Timeline Tools In A Methodology Toolbox Verification Methodology Reset Building Integrated Verification Flows – Round 2 AgileSoC.com Questa VRM is the New MS Project The Beginning Of The End For Coverage New Job Excitement

Joon Hong

Joon Hong - Questa Formal Product Engineer

Joon Hong is a Product Engineer on the Questa Formal team, with a focus on supporting customers with very large scale SoC ASIC and FPGA design and verification flows. In addition to his formal verification skills, Joon’s background includes simulation-based experience with SVA, UVM, low power (UPF), and clock-domain crossing (CDC) verification. Joon holds a Master's degree focused in Electrical, Electronics and Communications Engineering from Yonsei University.

Featured Session
How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

Thomas Ellis

Thomas Ellis - Senior Principal Product Engineering Manager

Thomas Ellis is a Senior Principal Product Engineering Manager at Siemens EDA for the Design Verification Technology division, specializing in the Questa Verification Management tool. Prior to joining the Design and Verification division, Thomas held the position of Applications Engineer in the Customer Support division. He holds a BSCS and BSEE from Oregon Institute of Technology.

Technical Papers
Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify Use Models Bringing Regression Systems into the 21st Century Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
Featured Sessions
Questa® Coverage Closure Accelerating Coverage Closure with a Plan
Verification Horizons
Increased Efficiency with Questa® VRM and Jenkins Continuous Integration

Stephen Bailey

Stephen Bailey -

As Director of Emerging Technologies, Stephen Bailey seeks out and develops new technology, solutions and business opportunities in functional verification and related areas. He brings many years of industry experience working in R&D, applications and technical and product marketing. He has contributed to the industry through participation in industry standards, including chairing VHDL (IEEE 1076) and UPF (IEEE 1801) working groups, and serving in various roles from member of technical program committee to conference chair with conferences such as DVCon. Prior to joining the EDA industry, Steve developed embedded software and software development tools. Steve has BS and MS degrees in computer science from Chapman University.

Featured Sessions
Validating Your SoC is True to Requirement Verification and Validation in the SoC Age FPGA Prototyping: Maximize Your Enterprise Debug Productivity Enterprise Verification Debug & Analysis Broad & Flexible Silicon Debug Visibility
Verification Horizons
Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs

Tom Kiley

Tom Kiley - Verification Technologist

Tom brings over twenty five years of EDA experience to Siemens EDA customers. Holding an electrical engineering degree from Gonzaga University, Tom has worked with several EDA vendors on research and development teams developing compilers and simulators, technical marketing, and currently as a product engineer for the QuestaSim product line. Tom also has spent many years developing and presenting training for customers as well as the Siemens EDA field staff. Outside of work Tom enjoys playing the guitar and drums, bicycling, and hiking as well as some electronics hobby work.

Course
UVM Debug
Product Demos
Visualizer™ Debug Environment
Featured Session
Simplifying Questa Usage and Deployment with Qrun

Raghu Ardeishar

Raghu Ardeishar - Verification Technologist

Raghu Ardeishar is a Verification Technologist at Siemens EDA for the Design Verification Technology division, specializing in Verification IP. He has 12 years of experience in the EDA industry, and has previously worked in the areas of HW design and verification. He has a Masters in Electrical Engineering from Virginia Tech.

Featured Sessions
Advanced Debugging with Assertions Effective Coverage using Assertions Questa® Verification IP PCIe Questa® Verification IP AMBA
Verification Horizons
Please! Can Someone Make UVM Easier to Use? Maximum Productivity with Verification IP Monitors, Monitors Everywhere – Who Is Monitoring the Monitors? Better Living Through Better Class-Based SystemVerilog Debug
Technical Papers
Are You Smarter Than Your Testbench? With a Little Work You Can Be UVM SchmooVM – I Want My C Tests! Monitors, Monitors Everywhere – Who Is Monitoring the Monitors Sequence, Sequence on the Wall – Who's the Fairest of Them All?

Dr. Jeremy Levitt

Dr. Jeremy Levitt - Principal Engineer

Dr. Levitt is a Principal Engineer in the Formal Verification Group of Siemens EDA. He oversees R&D with a focus on algorithm development. Jeremy earned his Ph.D in Electrical Engineering from Stanford in 1997, M.S. in 1993 and a B.A.Sc in Engineering Science from the University of Toronto in 1991.

Featured Sessions
Should I Kill My Formal Run? Part 1: Formal Run is In-Progress It’s Been 24 Hours - Should I Kill My Formal Run? Instant Formal Expert
Verification Horizons
Deadlock Prevention Made Easy with Formal Verification

Dave Aerne

Dave Aerne -

Dave Aerne is a Verification Technologist at Siemens EDA for the Design Verification Technology Division, focusing on Questa Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois, Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado. Dave is based in Portland, Oregon.

Featured Sessions
Questa® VIP Integration Questa® Verification IP Configurator Demo
Featured Article
Fast Track to Productivity Using Questa® Verification IP

Avidan Efody

Avidan Efody - Verification Architect

Avidan Efody is a verification architect for Siemens EDA, and an expert in listening to customers, distilling their problems, and helping them get to the optimal solution, preferably using Siemens EDA tools. Prior to moving to EDA Avidan has been architecting and coding testbenches in a variety of languages/methodologies for a variety of companies including PMC-Sierra, Infineon, TI, Nokia-Siemens and others. Recent problems he has been called to solve are fault analysis according to ISO 26262 specification, removal of adoption barriers for advanced verification methodologies within ISO 26262 and DO 254 flows, AMBA interconnect verification, Matlab-RTL integration and a few more. He’s proficient in SystemVerilog, OVM, UVM and a multitude of scripting languages such as Perl, TCL, PHP and JavaScript.

Resources
ISO 26262 Fault Analysis – Worst Case is Really the Worst Getting ISO 26262 Faults Straight Wiretap your SoC - Why scattering Verification IPs throughout your design is a smart thing to do

Geir Eide

Geir Eide - Product Marketing Director

Geir Eide is the product marketing director for the Tessent Design-for-Test software products at Siemens EDA. As a 20 year-veteran of the test and DFT industry, Geir has worked with leading semiconductor companies and presented technical presentations and seminars on DFT, test, and yield learning throughout the world. Geir earned his MS in Electrical and Computer Engineering from the University of California at Santa Barbara, and his BS in microelectronics from the University of South-Eastern Norway.

Featured Session
Tessent: DFT Enablement for AI Devices

Jin Hou

Jin Hou - Formal Specialist

Ms. Jin Hou received her Ph.D in formal verification from Université de Montréal. She is currently a product engineer for Questa Formal at Siemens EDA. She has 13 years working experience in Formal Verification and Assertion-based Verification, 8 years as CAE supporting the formal tool Magellan at Synopsys, and 5 years as a Product Engineer at Siemens EDA supporting Questa® AutoCheck, PropCheck, Cover Check, X-Check, Connectivity Check, Register Check, Secure Check, SLEC. She has been working in product definition, customer support, tool testing, customer training, technical marketing. She has applied formal verification to a lot of customer designs and helped worldwide customers adopt advanced technologies.

Course
Handling Inconclusive Assertions in Formal Verification Sequential Logic Equivalence Checking
Featured Sessions
Formal 101 – Data Independence and Non-Determinism Made Easy Formal 101 – Basic Abstraction Techniques Formal Verification: Automation and Tips for Success Should I Kill My Formal Run? Part 2: Avoid Trouble and Set Yourself Up For Success
Verification Horizons
Debugging Inconclusive Assertions and a Case Study

Ray Salemi

Ray Salemi - Aerospace and Defense Solutions Manager

Ray Salemi is the Aerospace and Defense Solutions Manager for Siemens Questa verification solutions. A former Mentor Graphics verification consultant working with aerospace and defense companies, Ray holds a Bachelor of Science in Computers Systems Engineering from the University of Massachusetts at Amherst and an MBA from Babson College. In his current role he ensures that Siemens IC verification solutions meet the needs of Aerospace and Defense companies.

Courses
Introduction to the UVM Evolving FPGA Verification Capabilities
Featured Sessions
Bringing Model-based Systems Engineering to IC and FPGA Design Easy Test Writing with a Proxy-driven Testbench The Digital Twin: An Aerospace and Defense Revolution Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Verification Horizons
Digital Thread, Digital Twin, and IC Development Hiding the Guts

Martin Rowe

Martin Rowe - Senior Applications Engineer

Martin Rowe is a Senior Application Engineer with OneSpin Solutions, a Siemens EDA business. Martin is an experienced technical sales and consulting engineer specializing in formal verification supporting a number of large customers. He is involved in the pre-sales process working with sales, marketing and R&D to ensure the successful adoption of solutions in the customer’s verification flow and methodology. Martin has a Master’s degree of Electrical Engineering from Northeastern University and a Bachelor’s degree from the University of Minnesota. Prior to OneSpin has worked from other EDA companies for the past 20+ years. Martin started his career as design engineer in the defense electronic industry.

Featured Sessions
Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Equivalence Checking for FPGA

John Hallman

John Hallman - Product Manager for Trust and Security

John is the Product Manager for Trust and Security at Siemens EDA. His work focuses on development of automated tools that check hardware designs for deliberate and unintended vulnerabilities that facilitate adversary attacks. John has 25 years of experience in the electronics industry. John is an active member in hardware standards including SAE G32, G19A, and the Accellera IPSA Working Group.

Featured Session
Securing the Electronics Development Chain with IC Integrity Solutions IP Security: Keys to Early Identification of Security Vulnerabilities

Vlada Kalinic

Vlada Kalinic - Product Specialist

Vlada Kalinic is the Product Specialist of EC-FPGA at Siemens EDA, and is involved in the evaluations with the new customers as well supporting the current portfolio of the customers to improve the current EC flows. Vlada has also another role, as SystemC Product Specialist in OneSpin. Vlada holds a master’s degree with honors in Electrical and Computer Engineering, Embedded Systems and Algorithms from the University of Novi Sad (Serbia). Prior to Mentor/Siemens, Vlada worked with OneSpin for 5+ years and was involved in various successful evaluations with SystemC and EC-FPGA customers.

Featured Session
Equivalence Checking for FPGA

Walter Gude

Walter Gude - Formal Product Specialist

Walter Gude is the Formal Product Specialist for Siemens EDA and responsible for promoting and deploying Questa Formal Solutions. Walter has over 30 years of experience in ASIC and FPGA design. He holds a Master’s of Science in Electrical Engineering from the Washington University in St. Louis. Walter worked for 10 years designing ASIC in the Telecom space. From there he went to work for Mentor Consulting and consulted on various ASIC projects including time spent in Munich, Germany, and Helsinki, Finland. For the next decade, Walter worked as an Application Engineer supporting Siemens EDA’s full suite of Functional Verification Products, before transitioning to his current role.

Featured Session
Automatic Formal Verification - Questa Static and Formal Apps

Stephane Hauradou

Stephane Hauradou - CTO

Stephane Hauradou cofounded PLDA - a leading supplier of high-speed Silicon IP - in 1996. Over the past 25 years, Mr. Hauradou has had many responsibilities in engineering and marketing, developing PLDA’s first PCI controller IP in 1996, and overseeing the transition to PCI-X and PCI Express.

Based in Silicon Valley, Stephane serves as a company Officer and Vice President, advising on corporate strategy and working day to day in product and technical marketing.

Byron Brinson

Byron Brinson - Application Engineering Consultant

Byron Brinson is a FuSa Field Technical Specialist at Siemens EDA. He has worked in FPGA design and verification for over 20 years. Of those years, 11 were spent specializing in Airborne Electronic Hardware certification. Byron is PMP certified and holds a Bachelor and Master degree in EE from Florida State University.

Featured Course
Introduction to DO-254

Hans Van Der Schoot

Hans Van Der Schoot - Verification & Emulation Technologist

Dr. Hans van der Schoot is a recognized specialist in verification technology, and employed as a methodologist in the Emulation Division at Siemens EDA. Hans has a solid background and wealth of knowledge in functional verification from his many years as a researcher, engineer and consultant in the field, with extensive practical experience providing verification methodology and implementation consulting and training services in the industry. He has authored multiple papers pertinent to hardware verification and software testing. Hans obtained his doctorate degree in computer science from the University of Ottawa, Canada, after graduating from the University of Twente in the Netherlands, also in computer science. Prior to joining Siemens EDA, he was the Vice President Engineering at XtremeEDA. He has also worked independently as an expert design verification consultant, following senior engineering positions with Qualis Design, PMC-Sierra, and Nortel Networks.

Course
SystemVerilog Testbench Acceleration
Verification Horizons
Bringing Verification and Validation under One Umbrella
Verification Patterns Library
BFM Notification Pattern BFM-Proxy Pair Pattern Dual Domain Hierarchy Pattern
Verification Resources
From Simulation to Emulation: 3 Steps to a Portable SystemVerilog/UVM Testbench Creating UVM Testbenches for Simulation & Emulation Platform Portability
Technical Papers
Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up Off to the Races with Your Accelerated SystemVerilog Testbench

Michael Horn

Michael Horn - Verification Architect

Michael Horn is a Principal Verification Architect at Siemens EDA specializing in helping ASIC and FPGA groups and companies to deploy UVM and OVM. He started his career in the telecom and storage industries doing design and verification. He has been using high level verification languages since 1999 starting with Specman E then moving to Vera and now SystemVerilog. Michael has co-authored numerous publications and conference papers including papers for DVCon. He received his BSEE from the University of Illinois at Urbana-Champaign.

Featured Session
UVMF & Emulation
Verification Horizons
Relieving the Parameterized Coverage Headache
Technical Papers
Verification Patterns - Taking Reuse to the Next Level Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning Parameters and OVM — Can’t They Just Get Along? Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program
Verification Patterns Library
Parameterized UVM Tests Pattern Utility Pattern
Verification Resources
UVM Cookbook

John Stickley

John Stickley - Verification Technologist

John Stickley is a Verification Technologist at Siemens EDA Emulation Division. His research interests are in electronic design verification methodologies. His most recent work at Siemens EDA has been in the area of high-performance emulation based verification techniques in particular with using SystemVerilog OVM/UVM and SystemC TLM-2.0 based testbench modeling - particularly in conjunction with the use of virtual processor platforms. He has 30 years of experience in the EDA industry and holds a BSEE degree from Cornell University.

Course
Testbench Co-Emulation: SystemC & TLM-2.0

Vijay Chobisa

Vijay Chobisa - Product Marketing Manager

Vijay Chobisa has over 15 years of experience in transaction-based acceleration and in-circuit emulation. He is currently the Product Marketing Manager for the Emulation Division at Mentor, A Siemens Business. He has worked as a technical marketing engineer and technical marketing manager at IKOS systems and as an ASIC design engineer at Logic++. Vijay holds a bachelor’s degree of electronics and communication engineering from Jai Narayan Vyas University, Rajasthan, India.

Featured Sessions
System Level SoC Verification and Validation Using Emulation and Prototype Platforms Market-Driven Trends in Hardware Emulation An Emulation Strategy for AI and ML Designs Emulation Platform Brings Unique Solutions to Automotive Market Accelerating UVM-based Verification from Simulation to Emulation
Verification Horizons
Three Main Components to Look for in Your Emulation Platform Emulation – A Job Management Strategy to Maximize Use

Dominic Lucido

Dominic Lucido - Formal Verification Technologist

Dominic has been with Mentor for 18 years and has focused on RTL verification and safety critical design and verification in his former role as an Applications Engineer consultant. Dominic is currently in the role of Formal Verification Technical Specialist supporting Mentor’s Formal Solutions.

Featured Session
Why Gate-Level CDC Is Needed (Even After RTL CDC Closure!)

Sathish Balasubramanian

Sathish Balasubramanian - Senior Product Manager

Sathishkumar Balasubramanian has over 15 years of experience in the EDA industry. At Mentor, Sathish is responsible for product management and marketing functions across Mentor’s AMS verification product portfolio driving mixed-signal & memory simulators and library characterization platform .Over the years, Sathish has held various roles ranging from design engineer, sales and marketing at Cadence and Synopsys. Before joining Mentor, Sathish was responsible for Product Marketing Management covering FastSPICE and Mixed-signal simulators at Synopsys. Sathish has a bachelor degree in Electrical engineering from University of Madras, MS in Computer engineering from University of Alabama and an MBA from UC Berkeley, Haas school of Business.

Featured Sessions
Improving Verification Throughput of Today’s Complex Mixed-Signal ICs with High-Level Model Abstractions AMS Verification Methodology for GPUs in AI and Deep Learning Applications Emerging Trends in AMS Verification Methodology for Automotive & IoT Devices

Vinayak Desai

Vinayak Desai -  Product Engineer

Vinayak Desai is a Product Engineer at Siemens EDA and is responsible for defining the requirements of the new features for Questa Design Solutions. He holds a Master of Science from California State University at Northridge. Prior to Siemens EDA, Vinayak has held various positions at Synopsys, Magma and Cadence as a Field Application Engineer and at Nokia as a design support engineer.

Featured Session
Questa Design Solutions as a Sleep Aid Exploration into Safety Analysis Techniques That Optimize the Safety Workflow

Dr. Ashish Darbari

Dr. Ashish Darbari - CEO

Dr. Ashish Darbari is the founder & CEO of Axiomise – a formal verification training, consulting, services, and IP company. Ashish has trained close to 200 engineers in formal verification across some of the best-known names in the industry. He is the author of the formalISA® app and runs a podcast channel "Formal Bytes" to promote the very best in verification. Ashish has 38 patents in formal verification and 77 publications. He holds a DPhil in formal verification from the University of Oxford and has been a Royal Academy of Engineering Visiting Professor at the University of Southampton and is also a Fellow of the British Computing Society, and IETE.

Featured Session
The ABC of Formal Verification
Verification Horizons
Predictable and Scalable End-to-End Formal Verification Formal Verification of RISC-V® Processors

Cliff Cummings

Cliff Cummings - President - Sunburst Design

Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world class Verilog, SystemVerilog, UVM Verification and synthesis training. Mr. Cummings is an independent consultant and trainer with 33 years of ASIC, FPGA and system design experience and 23 years of Verilog, SystemVerilog, synthesis and methodology training experience. Mr. Cummings has completed many ASIC designs, FPGA designs and system simulation projects, and is capable of answering the very technical questions asked by experienced design engineers.

Featured Sessions
What's Missing and What Should Be Next for SystemVerilog Virtual Method Upcasting & Downcasting And Their Use In UVM C'mon ... Quit Screwing-Up the UVM $display Command!! SystemVerilog Assertions - Bind files & Best Known Practices UVM Message Display Commands SystemVerilog Assertions Design Tricks SystemVerilog Concurrent Assertions

Gordon Walker

Gordon Walker - Senior Product Manager

Gordon Walker is currently a Senior Product Manager within the ICVS Business Unit of Siemens EDA.

Featured Session
SoC Verification Problems From Early Software to System Implementation

Didan Francis

Didan Francis - USB Product Engineer

Didan Lazar Francis is a Product Engineer for USB at Siemens EDA, focusing on deployment and product definition of Questa Verification IP. Francis has over 10 years of experience in the functional verification domain, with a background in developing industry standard interface protocols using the UVM methodology.

Featured Resource
Creating a Fast and Productive USB4 Verification Environment

Munish Goyal

Munish Goyal - QVIP Product Engineering

Munish Goyal has spent almost 15 years in Pre-Silicon verification and post silicon validation, working at top semiconductor companies like Qualcomm, Freescale & ST Microelectronics. He holds a bachelor’s degree in Electronics & Communication from a premier institute in India. He spent good amount of his time doing SoC verification for ARM-based designs, developing expertise in CPU and peripheral verification before he moved into EDA, focusing on VIPs. For the past 10 years, Munish has been involved in the development and deployment of advanced Verification IPs. At Mentor, Munish leads the Questa Verification IP (QVIP) Product Engineering teams worldwide.

Featured Session
Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP

Brian Craw

Brian Craw - Senior Staff CAD Engineer

Brian is a Senior Staff CAD Engineer with Cypress Semiconductor. His background includes RTL design/verification/integration of image processing IP into multi-core ARM based SoC's, SystemVerilog based constrained random test environment development, post-silicon validation, and firmware development for embedded platforms.

Feature Session
Using Automation to Close the Loop Between Functional Requirements and their Verification

Ashish Amonkar

Ashish Amonkar - Principal Electrical Engineer

Ashish joined Cypress as a NCG from University of Colorado, Boulder with a M.S.E.E. Ashish transitioned from doing design and layout for Cypress SONOS Flash memory subsystems to doing mixed signal verification on PSoC3/5 chips using Questa ADMS. Ashish has successfully led the mixed signal verification effort on Cypress SONOS Flash Memory Subsystems across the various technology generations. With the advent of OVM and UVM methodologies Ashish started deploying these methodologies to make the System Resources test bench highly scalable and reusable across multiple variants of the design. Ashish has also successfully set up the Questa Power Aware Methodology on the System Resources block to accelerate the UPF verification closure across the various parameters in the design as well as complex power domain interactions. Ashish has vast experience of all phases of verification across digital, mixed signal and fast spice domains. He holds three patents in Flash memory design and systems as well.

Power Aware Simplifies Parametric PA-SIM Regression

Andreas Meyer

Andreas Meyer - Verification Architect

Andreas Meyer is a Verification Technologist with Siemens EDA, focusing on functional verification methodology. Andy was one of the developers of OVM, is the author of Principles of Functional Verification, and has been a consultant in the design and verification space for many years.

Course
Metrics in SoC Verification
Verification Horizons
Graph-Based IP Verification in an ARM SoC Environment
Resources
So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results

Lee Harrison

Lee Harrison - Automotive IC Test Solutions Manager

Lee has over 20 years of industry experience with Tessent DFT products and has been involved in the specification of new test features and methodologies for Siemens customers, delivering high quality DFT solutions. With a focus on automotive, Lee is working to ensure that current and future DFT requirements of Siemens’s automotive customers are understood and met. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996.

Featured Session
Achieving High Defect Coverage for Safety Critical and High Reliability Designs

Srikanth Rengarajan

Srikanth Rengarajan - Vice President, Products & Business Development

Srikanth brings over 20 years of technology practice across automotive, mobile and embedded systems. He joined us from Broadcom Corporation where he held leadership roles in architecting, developing and marketing processor subsystems. His domain expertise in automotive gateways, Point-of-Sale, Biometric and VoIP applications provide him unique insights to the challenges of security, safety and reliability facing developers of mission-critical compute systems. Previously he served as product line leader at Advanced Micro Devices where he led their charge into Ultra Low Power client segment. Srikanth’s pedigree include development of the XScale mobile architecture at Intel and SPARC CPU development at Ross Technology. He holds a Bachelor’s in Electrical Engineering from the Indian Institute of Engineering, Madras, a Master’s in Applied Physics from the Oregon Health and Sciences University and an MBA from the McCombs’ Schools of Business at the University of Texas at Austin.

Featured Session
Demonstrating Functional Safety Compliance in Automotive IC Design

Ram Narayan

Ram Narayan - Hardware Development Senior Manager

Ram Narayan is a Consulting Member of Technical Staff in Oracle Labs. He is a member of the RAPID SoC Hardware Verification Team since January 2013. Prior to joining Oracle, Ram was a Principal Member of Technical Staff in the Platform Emulation Team at Advanced Micro Devices. In this capacity, he was driving improvements to the pre-silicon emulation strategy to impact the post-silicon validation effort and reduce the time to market. Ram joined AMD from Mentor Graphics in 2010. As an Application Engineer at Mentor Graphics, he helped Mentor's customers realize their verification goals with a range of technologies including Simulation, Formal Verification, Assertion and Coverage Based Verification, Testbench Automation, Hardware Software Co-verification and Hardware Emulation. Ram has 26 patents granted in the US. Ram received a B.Tech. in Electrical Engineering at The Indian Institute of Technology, Bombay in 1991 and an M.S. in Computer Engineering at The University of Texas at Austin in 1994.

Featured Session
Formal Model Checking: From Oblivion to a Pillar of Success
Verification Horizons
Evolving the Use of Formal Model Checking in SoC Design Verification

Rick Koster

Rick Koster - Low Power Specialist

Rick Koster is the North America Low Power Specialist for verification tools at Siemens EDA. Rick started his career at Texas Instruments as a microcontroller application engineer. He has held engineering positions at the US Army, Bytex Corporation and for almost 25 years has worked in verification applications at Siemens EDA through Mentor Graphics and Ikos Systems.

Featured Session
Low Power Considerations for Verification

Larry Lapides

Larry Lapides - VP Sales

Larry currently runs worldwide sales at Imperas Software Ltd., and previously ran worldwide sales at EDA companies Averant and Calypto. He was vice president of worldwide sales during the run-up to Verisity’s IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Larry has been on the Clark University Graduate School of Management (GSOM) Advisory Council since 2003, and was an Entrepreneur-in-Residence at Clark during Fall 2006, when he developed and taught the course on Entrepreneurial Communication and Influence. Larry holds a BA in Physics from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and a MBA from Clark University.

Featured Session
RISC-V Core and SoC: Compliance, Verification, Customization
Verification Horizons
The Six Steps of RISC-V Processor Verification Including Vector Extensions Extending SoC Design Verification Methods for RISC-V Processor DV

Marc Schmitz

Marc Schmitz - Imaging IPs Design Manager

Marc manages the digital design and verification teams in STMicro Imaging division, which is focused on Image Sensor and Time-Of-Light products for consumer and automotive markets. After a Dipl.-Ing.degree from Phelma School in Grenoble, Marc started in STMicro in 2004 as a verification engineer and worked on many projects such as Microcontroller or Multimedia Engine for Application Processor. His technical expertise encompasses verification and design flows including High-Level Synthesis introduced in 2007 in the design process.

Featured Session
Low-Power Design using High-Level Synthesis for Automotive Image Sensor

Kartik Raju

Kartik Raju - Senior Manager VLSI

Kartik Raju is a Senior Manager VLSI at Knowles where he leads the digital ASIC team developing advanced voice and audio processor IP. He has two decades of experience in SoC design and verification. Most of his experience has been in design and verification roles in Wireless and Audio product development. He was the lead verification engineer in adopting UVM methodology at Knowles. He is currently leading the team from concept to production which includes managing chip Architecture, design, verification and physical implementation. He is passionate about automation and adopting new methodologies to shorten the development cycle in this complex feature requirement and time to market environment.

Featured Session
My Experience with Questa® CDC Bring-Up

Qazi Ahmed

Qazi Ahmed - Product Marketing Manager

Qazi Ahmed is the Product Marketing Manager for PowerPro at Siemens EDA. He has over 14 years of experience of which about 10 years is in EDA, spanning organizations like Cadence and Atrenta (Synopsys). Qazi had been an Application Engineer for PowerPro in South Korea for 3+ years where he drove PowerPro growth with key customers. Qazi has also been an FPGA Designer in the past with a background in Aerospace & Defense.

Featured Session
Deploying A Metrics Driven Low Power Methodology for Your RTL IP

Harmel Sangha

Harmel Sangha - Director ASIC Engineering

Harmel Sangha is an engineering director at Micron Technology where he leads an ASIC team developing advanced high performance interface IPs for SSD controllers. He brings over two decades of enterprise product development experience with accentuated focus on right first time execution methodologies. His career spans engineering and marketing leadership roles in high speed serial technology development and deployments. His teams have enabled first to market Fibre Channel, PCI Express and Ethernet products in enterprise storage, compute and networking applications, addressing next generation challenges in the data center infrastructure. His passions include creating highly effective teams with a focus on predictable and repeatable project execution by adopting emerging engineering methodologies such as UVM.

Featured Session
UVM Enabled Advanced Storage IP Silicon Success

Sriram Hariharan

Sriram Hariharan - Principal Engineer

Sriram Hariharan is working as a principal engineer/manager in Qualcomm. He has 14+ years of experience in ASIC verification and low power verification. He is the lead power verification methodologist for Qualcomm worldwide DV teams and verification architect for UPF adoption and its extensions. He manages power verification team for various Snapdragon platforms.

Featured Session
Industry Advancements Required to Close the Power Management Verification Gap

Shantanu Samant

Shantanu Samant - Technical Marketing Engineer

Shantanu Samant is a Technical Marketing Engineer at Siemens EDA in the Emulation Division. He’s in his 10th year of the Semiconductor Industry with 8 years spent at Siemens EDA as an Emulation Specialist. He focuses on helping users get the most out of their emulators with the help of various features, one of them being Veloce Power App.

Featured Session
Low Power Verification & Analysis with Emulation

Sanjay Gupta

Sanjay Gupta - Senior Director of Product Engineering

Sanjay Gupta is a Senior Director of Product Engineering and Flows & Methodologies for the ICVS Division of Siemens EDA. He was previously an Engineering Director at Qualcomm Technology, Inc. where he led the SoC Verification Team. His responsibilities included SoC Verification Methodology, SoC System Level Verification using Simulation, Acceleration, FPGA, and Power Verification. He has over 25 years of experience most of which are in the Verification area. He spent most of his career at IBM with additional positions at Synopsys, ARM and Freescale. Most of his background has been focused on Processor Verification. He also spent significant time and effort working on Methodology at various companies.

Featured Session
UVM and Emulation: Easing the Path to Advanced Verification and Analysis

Jim Lewis

Jim Lewis -

Jim Lewis, the founder of SynthWorks, has twenty-eight years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis does ASIC and FPGA design, custom model development, and consulting. Mr. Lewis was previously employed with Zycad's Protocol division where he worked as an on-site VHDL trainer, methodology consultant, and ASIC designer. As a representative from Zycad, he provided VHDL training, methodology consulting, and ASIC design for Lockheed Sanders in their development of 22 ASICs for the F22 program. On another assignment for Zycad, he worked as a VHDL trainer, Synopsys synthesis trainer, problem solver, and ASIC designer for SGS Thomson in their development of a Video Codec chip. In addition to other responsibilities, Mr. Lewis acted as an on-site focal point for resolving VHDL synthesis issues for both companies.

Mr. Lewis was also employed by TRW where he designed ASICs, FPGAs, and worked as a member of their VHDL Methodology Development Group. Mr. Lewis, who holds a BSEE/BSCEE and MSEE from Purdue University, is a member of the IEEE and the Eta Kappa Nu, and Tau Beta Pi Honor Societies. Mr. Lewis is chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG) and is an active member in IEEE and Accellera's VHDL standardization efforts. Mr. Lewis is also co-author of VHDL-2008: Just the New Stuff and recommends The Designer’s Guide to VHDL and the VHDL-2008 LRM.

Course
VHDL-2008: Why it Matters
Verification Horizons
Addressing VHDL Verification Challenges with OSVVM VHDL-2008: Why it Matters

John Aynsley

John Aynsley - CTO, Doulos

John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specializing in simulation, languages (particularly VHDL, SystemVerilog, and SystemC), hardware verification and system modeling, and has written many training courses and technical papers in these areas. He is co-author of the IEEE 1666 SystemC standard, author of the OSCI TLM-2.0 LRM, and an active contributor to several technical working groups and forums. His current role spans technical consulting, technical marketing, and business management.

Featured Session
Portable Stimulus versus UVM: What's the Difference?
Course
Basic OVM

Anupam Bakshi

Anupam Bakshi -

Anupam is the founder and CEO at Agnisys. He has more than two decades of experience implementing a wide range of products and services in the High Tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel Corporation, Blackstone Consulting Group, Cadence Design Systems and Gateway Design Automation. Anupam has earned a HighTech MBA from Northeastern University, Massachusetts, a Master’s in Computer Engineering also from Northeastern University and a Masters in Science (Electronics) from Delhi University.

Featured Sessions
Auto-Generation of Implementation-Level Sequences for PSS Specification to Realization flow using ISequenceSpec™ and Questa® inFact

Dr. Mike Bartley

Dr. Mike Bartley -

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering and an MBA from the Open University, and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies (including STMicroelectronics, Infineon and Elixent/Panasonic) who still use the methodologies he established. Since founding TVS he has consulted on multiple verification projects for respected organisations including ARM and Infineon.

Dr. Bartley is currently Chair of the Bristol branch of the British Computer Society and Chair of the High Tech Sector Group of the West of England Local Enterprise Partnership (LEP) and is a Technical Advisor to the National Microelectronics Institute (NMI). He has had over 20 articles published on the subject of verification and outsourcing.

Featured Session
Verifying Safety-Related Systems

Vahid Naraghi

Vahid Naraghi - Senior Manager of ASIC Engineering
  • Senior Manager of ASIC Engineering at Brocade (BRCD) Communications Based in San Jose, California
  • 20 years of digital Design and Verification experience
  • Graduated from Rice University in Houston TX (BSEE and MSEE)
  • Hold several patents in network switch technologies
  • Enjoys scuba diving, skiing, mountain climbing, sky diving, tennis, bball...
Featured Session
Next Generation Debug Experience with Visualizer Debug

Vigyan Singhal

Vigyan Singhal - President and CEO

Vigyan Singhal is president and chief executive officer of Oski Technology, responsible for overall leadership of the company. He has worked in the semiconductor and EDA industries for more than 20 years, having led two venture-funded start-ups – Jasper Design Automation (acquired by Cadence) and Elastix (acquired by eSilicon). Vigyan started his career as a Research Scientist at Cadence Berkeley Labs. He has authored more than 70 publications, and holds 14 patents in IC design and verification. Vigyan has a PhD in EECS from the University of California at Berkeley where he was a Regents Scholar, and has a BTech in Computer Science from IIT Kanpur where he graduated at the top of his class.

Featured Session
Using a Chessboard Challenge to Discover Real-world Formal Techniques

Jin Zhang

Jin Zhang - VP of Marketing and Customer Relations

Jin Zhang, VP of Marketing and Customer Relations, Oski Technology has over 15 years of experience working in EDA, driving the effort of bringing new products and services to market. At Oski, she is responsible for the overall marketing strategy as well as business development in Asia Pacific. Prior to that, she was the General Manager at EVE China, and Director of Technical Marketing at Real Intent. She has also worked at Cadence Design Systems and Lattice Semiconductor. Jin has a PhD in logic synthesis and verification and a Master’s degree in International Management focusing on Asia Pacific.

Featured Session
Starting Formal Right from Formal Test Planning

Mitchell Poplingher

Mitchell Poplingher - Senior Manager, Verification

Mitchell Poplingher is a Senior Manager, Verification in the SoC Division at Microsemi Corporation.

Featured Session
An Exhaustive 1-2 Punch for RTL Signoff

Niraj Mathur

Niraj Mathur - Vice President of High Speed Interface Products

Niraj Mathur is Vice President of High Speed Interface Products at Rambus. He has 20 years of industry experience in advanced SOC & IP design, verification, software and leading cross-functional, global engineering teams. He has also established applications engineering and program management organizations. In his current role, Niraj leads new initiatives in a marketing capacity and is focused on expanding Rambus' chip product business.

Niraj's career spans large, medium and startup technology companies. He was instrumental in delivering several successful products ranging from one of the world's first 10 Gigabit Ethernet devices to complex silicon for telecom switches and metro optical networks.

Niraj holds a Bachelor of Computer Engineering degree from McGill University and an MBA from Cornell University.

Featured Session
Trends and Requirements in High Speed Interface Verification

Dinesh Tyagi

Dinesh Tyagi - President & CEO

Dinesh Tyagi is currently the President & CEO of Innovative Logic. Dinesh has spent 20+ years in different engineering, marketing, and sales roles before starting Innovative Logic. He founded Innovative Logic in 2005. Prior to Innovative Logic, Dinesh was working as senior marketing person in Altera’s IP division. Before Altera, he was responsible for application engineering and marketing for high end micro-controllers in Renesas. Before joining Renesas, Dinesh spent two years in a embedded CPU startup company performing many challenging roles in marketing, and application engineering. Dinesh also successfully managed Application Engineering group in Synopsys. Prior to Synopsys, Dinesh spent 4 years in ST Microlectronics and 2 years in Cadence in different engineering roles.

Featured Session
USB 3.1 Verification Challenges

Ellie Burns

Ellie Burns -

Ms. Burns has over 25 years of experience in the chip design and the EDA industries in various roles of engineering, applications engineering, technical marketing and product management. She is currently the Product Manager in the Design and Verification Technology Division at Siemens EDA responsible for simulation with Questa and ModelSim. Prior to Siemens EDA, Ms. Burns has held engineering and marketing positions at CoWare, Cadence, Synopsys, Viewlogic, Computervision and Intel. She holds a BSCpE from Oregon State University.

Featured Sessions
Using HLS to Accelerate Computer Vision for Autonomous Drive Successive Refinement: A Methodology for Incremental Specification of Power Intent using UPF Cadence and Mentor Kickoff Collaboration for open Debug Data API New Low Power Verification Techniques
Industry Articles
Syncing Up CDC Signals in Low Power Designs Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard Shifting Low Power Verification to an IP to SoC Flow Something Old, Something New…EDA and Verification

Akshay Sarup

Akshay Sarup - Verification Technologist

Akshay Sarup is Verification Technologist for Siemens EDA Design Verification Technology Division. He has extensive experience in Verification IP deployment and development. He is an expert in protocols like PCIe, NVMe, Ethernet, AMBA family and has over 17 years of experience in Design Verification Software development.

Featured Sessions
A Guide to QVIP Workflow and Debug for PCIe Enterprise Ethernet PHY Verification Need for Speed - PCIe GEN4 Verification
Verification Horizons
PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA Application

Peet James

Peet James - Sr. Verification Consultant

Peet James was recently described by a customer as a “Verification Animal”. Over his 25+ years of experience he has always had one foot entrenched in improving both design and verification methodologies and processes, and the other foot entrenched in directly applying these to actual projects. Peet’s specialty is verification planning and management where he typically takes a team of engineers and guides them into architecting, documenting and implementing successful verification environments. Peet started out working at Sperry, IBM & Motorola, and then moved into consulting as one of the principles at Qualis Design Corporation. Peet has been with Mentor Graphics for the past 3 years. Peet has many award winning papers and is a published author of a book on verification planning.

Course
Verification Planning and Management

Ivan Ristic

Ivan Ristic - ASIC Verification Engineer

Ivan Ristic is currently a senior verification engineer at HDL-DH. Mr. Ristic graduated from the Faculty of Technical Sciences at the University of Novi Sad, where he received his M.Sc. degree. Since joining HDL Design House in 2007, his main responsibilities are leading and managing teams that work on design verification for various customers' IPs and SoCs.

Featured Session
MIPI® CSI-2 TX Verification
Verification Horizons
MIPI® CSI2 TX IP Verification Using Questa® VIPs

Peter Wang

Peter Wang - Verification Platform Project Leader

Peter Wang is currently the Marvell QVIP UVM Verification Platform Project Leader for PHY chip verification. He has over 15 years of experience designing and verifying ASICs & ARM based SOCs. Currently he is focused on the UVM Design Verification for Marvell PHY chips. He has published multiple papers of ASIC UVM design verification on IEEE publications and was a special invited speaker in the 2017 Mentor QVIP international users forum. Previously to Marvell, he was a principle ASIC engineer at Broadcom, SoC Architecture Engineer at Intel Corporation, and a project leader for multiple SoC starting-up companies.

Featured Session
Where No Man Has Gone Before: Enterprise Ethernet PHY Verification

Brian Mathewson

Brian Mathewson - Verification Technologist

Brian Mathewson is verification technologist focused on enabling highly efficient verification of FPGAs. He has over 15 years’ experience designing and verifying ASICs and FPGAs. Brian has worked as an FPGA designer, verification engineer, and verification lead for small and large teams. Much of Brian’s career was at SEAKR engineering where he worked on large memory controllers and DSP heavy satellite communication ASICs. Brian also worked as the verification architect in Micron’s SSD controller division deploying UVM to verify large SoCs.

Featured Session
Coverage & Plan-Driven Verification for FPGAs

Adam Rose

Adam Rose - Product Marketing Manager

Adam Rose is the Product Marketing Manager for Questa Verification IP. He was the author of the SystemC TLM 1.0 and the main technical contributor to the Advanced Verification Methodology (AVM), which was the first open source SystemVerilog verification methodology. He also managed the team that developed the UVM Cookbook on Verification Academy. He went on to lead Mentor’s VIP engineering team before moving into his current role.

Featured Session
One Stop Verification IP Memory Library

Chuck Seeley

Chuck Seeley - Verification Technologist

Chuck Seeley has over 27 years of experience in engineering design and verification, and technical marketing. As a Technical Marketing Engineer at Siemens EDA, he specializes in both assertion-based verification and coverage driven verification methods. He holds a BSEE from Portland State University.

Course
Power Aware Verification
Featured Sessions
Questa® Power Aware Visualizer Demo Questa® Power Aware Simulation Demo Questa® Simulation Demo New Low Power Verification Techniques
Resources
Debug Challenges in Low-Power Design and Verification

Erich Marschner

Erich Marschner - Verification Architect

Erich Marschner has more than 30 years of experience developing language-based tools, systems, methodology, and industry standards for electronic systems design and verification. Currently, Erich is a Verification Architect with the Design Verification and Technology Division at Siemens EDA and vice-chair of the IEEE 1801 UPF working group.

Course
Power Aware Verification
Verification Horizons
The Evolution of UPF: What’s Next? Evolution of UPF: Getting Better All the Time
Resources
Understanding Coverage Holes Multi-Domain Verification: When Clock, Power and Reset Domains Collide Unleashing the Full Power of UPF Power States

Ahmed Eisawy

Ahmed Eisawy - Technical & Product Marketing

Ahmed Eisawy is a member of the Technical & Product Marketing team of the Analog/Mixed-Signal group – part of the Deep Sub-micron Division – at Siemens EDA. For the last five years, he’s been working as a member of the marketing team to drive the development of Analog/Mixed-Signal simulators forward with new technologies as well as engage with customers for evaluations, training & education, solving complex problems as well as help the customers through methodology assessments to improve their flow. Previously, Ahmed worked for seven years in technical support where he worked closely with customers, helping resolve problems and help formulate the customer needs into tool enhancements. He received his BSEE from Cairo University in 1999 and his MSEE from the same university in 2002.

Courses
AMS Design Configuration Schemes Improve AMS Verification Performance Improve AMS Verification Quality
Verification Horizons Article
Improving Analog/Mixed-Signal Verification Productivity

Verification Academy

Verification Academy -

Mentor's Verification Academy is a first of its kind—unlike anything in the industry. Its goals are to provide the skills necessary to mature an organization's advanced functional verification process capabilities. To this end, the Verification Academy provides a methodological bridge between high-level value propositions (related to advanced verification technology) and the low-level details (related to specific tool and verification language details).

Featured Seminar
User2User Silicon Valley 2019
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