Release date: April 25th, 2023.
Now that our acquisition of Avery Design Systems is complete, Siemens EDA are the new leaders in Verification IP in the industry. Our combined team of experts are ready to provide the industry with a complete protocol and memory verification portfolio, to bring independent, high quality verification, standards-based solutions that are interoperable across all simulators, and quality which is already trusted by the most successful silicon teams across the globe.
This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications. We are ready to challenge the status quo of yesterday’s aging memory models and protocol solutions. Are you ready?
This session will include a demonstration of the VIQ functionality that its users routinely benefit from.
What You Will Learn:
- The breadth of the Siemens EDA protocol and memory verification portfolio
- The depth of verification IP solutions including comprehensive models and test suites
- Solutions spanning module to subsystem to chip level to system level stimulus and checking
- The expertise you need as a partner for your 2.5D / 3DIC / chiplet project using UCIe protocol
Who Should Attend:
- Design Verification Engineers and Managers
- RTL Design Engineers and Managers
- 3DIC/2.5DIC/Chiplet/SiP/SoC Architects
Which Product(s) are Covered:
