PSS aims to help users describe the high-level test intent and generate code for various verification platforms. In order to further enhance portability, by design PSS avoids the implementation details. This means users have to manually code long and complex hierarchical test sequences for IP and SoC tests in different languages such as C, SystemVerilog or CSV. In this presentation, we will show a unique solution based on the integration of iSequenceSpec with Questa inFact. The implementation-level sequences can be captured by the user in pseudo code using a Python text-based environment and generate the target sequence code to be used for simulation, emulation, firmware tests and post-silicon validation. The solution synchronizes multiple SoC groups to work from a golden spec - critical to today’s SoC projects. With the ability to parse register and memory maps in SystemRDL, IP-XACT or CSV, users are able to exercise the hardware/software interface through register read/writes and bus transaction-level messages.
