You've written 1000's of constraints, assembled several testbenches, written coverage models, and run 100's of simulations to verify your IP blocks. You've achieved nearly 99% code coverage and even 95% of your functional coverage. You've even run SoC level emulations runs, and found (and repaired) several hardware software integration problems. But when you get to the lab, you still see intermittent design performance problems. This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.