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Verification Academy Live Hudson

Seminar - Jun 09, 2026 by Joe Hupcey

This seminar will provide design engineers and verification teams with the knowledge and tools needed to advance their workflows using the latest AI-driven automation, intelligent verification platforms, and industry-proven methodologies. Tuesday, June 9, 2026 | 9:00 AM - 5:00 PM EDT Location American Heritage Museum 568 Main St Hudson, MA 01749 +1 (978) 562-9182 This event is in-person only — there is no support for remote participation.
Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

Webinar - May 20, 2026 by Tufail Ansari

In this webinar, we will talk about PCIe Gen8 Retimer and Optical retimer, and its key applications, which includes use of optical retimer in GPU and AI accelerators. Further, we will explain the Four-Retimer Aware (FRA) feature and the rules that apply to loopback, lane margining and SKP ordered sets.
Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

Resource (Slides (.PDF)) - May 20, 2026 by Tufail Ansari

In this session, we will explain the Four-Retimer Aware (FRA) feature and the rules that apply to loopback, lane margining and SKP ordered sets.
Generating Quality Properties for Formal Verification of a Design

Webinar - May 19, 2026 by Gerardo Nahum

Improve productivity by generating properties using AI and enable on‑the‑spot syntactic and semantic verification. In this webinar, we will demonstrate how Questa One SFV provides critical prompts for AI agents and LLMs to produce usable properties. This session highlights seamless integration with VS Code, enabling property generation, property checking, and interactive property debugging within a familiar development environment.
Verification IP: Why Design Teams Buy Instead of Build

Resource (Verification Horizons Blog) - May 18, 2026 by Gordon Allan

Verification IP is one of those categories that sounds simple until a project tries to live without it. As interface standards become more complex, design teams face a familiar decision: build protocol and memory verification infrastructure internally or buy a reusable solution that is already aligned to the standard. For many teams, that decision affects schedule, engineering focus, and verification confidence just as much as it affects tooling.
Optimizing Functional Fault Grading Flow for Memory Designs with Questa One Sim FX

Conference - May 12, 2026 by Seong Wook Lee

In this User2User Europe session, you will learn about an advanced fault simulation flow for memory design (DRAM). Accomplishing bridges the gap between TR-level design complexity and high-performance gate-level fault grading using Questa One Sim FX. To overcome various challenges and accelerate simulation speed, we implemented a strategic Design Pruning and diverse optimization techniques. we successfully mitigated the runtime bottlenecks typically associated with exhaustive fault analysis.
Automated Requirement Driven, SystemVerilog-based Verification Workflow for Mixed-Signal ASICs

Conference - May 12, 2026 by Vincent Camus

In this User2User Europe session, you will be introduced to a FuSa workflow connecting ASIC development using Siemens Polarion requirements management with advanced SystemVerilog verification and chip-level mixed-signal validation. This approach ensures robust sign-off and coverage across analog and digital domains while maintaining strict design-to-requirement alignment by integrating specifications and verification items into VIP-based SystemVerilog testbenches and assertions.
Shift Left at Scale: Siemens Factory Automation’s Journey to Consistent RTL with Questa Lint

Conference - May 12, 2026 by Dominik Mentel

In this User2User Europe session, you will learn that Siemens Factory Automation successfully adopted Siemens EDA Questa Lint to strengthen RTL quality and support a modern CI/CD driven development flow. This session highlights how Questa Lint was integrated into Siemens Factory Automation’s design workflow, unexpected RTL issues uncovered, highly configurable checks and centralized rulesets enabled consistent coding practices.
Verifying a 3DIC IP with Avery UCIe and the Questa One Sim Workflow

Conference - May 12, 2026 by Niels Burkhardt

In this User2User Europe session, you will learn that a crucial element of a verification methodology involves using Avery Verification IP's callback mechanism to implement specialized error checking at the PHY level. Furthermore, full UCIe compliance is ensured through the use of the provided UCIe compliance suite. We will also highlight how the debugging features of the Avery Verification IP and Questa One are instrumental in achieving a successful verification outcome.
From Workflow Reality to AI Productivity: Lessons from Philips Engineering

Conference - May 12, 2026 by Serkan Oktem

In this User2User Europe session we present practical lessons from introducing AI into complex Philips engineering workflows. We discuss what worked, where limitations appeared, and how aligning AI capabilities with existing developer environments and constraints is key to achieving sustainable productivity gains in collaboration with EDA partners.
Agentic AI for RTL Signoff Part 2: Questa One Agentic Toolkit

Conference - May 12, 2026 by Frank Armbruster

In this User2User Europe session we will translate AI potential into sustainable productivity improvements for engineers by demonstrating practical lessons from introducing AI into complex Philips engineering workflows. We discuss what worked, where limitations appeared, and how aligning AI capabilities with existing developer environments and constraints is key to achieving sustainable productivity gains in collaboration with EDA partners.
Agentic AI for RTL Signoff Part 1: Questa One Agentic Toolkit

Conference - May 12, 2026 by Darron May

In this User2User Europe session we will demonstrate how the Questa One Agentic Toolkit - announced in February 2026 and built on the industry-leading Questa One verification solution - transforms verification from isolated applications into intelligently orchestrated workflows through purpose-built Agentic AI that autonomously reasons, plans, and executes strategies while keeping engineers in the loop with approval controls at critical decision points.
Join Me at DVClub Austin - May 20, 2026

Resource (Verification Horizons Blog) - May 11, 2026 by Harry Foster

The semiconductor industry is entering one of the biggest transitions I’ve seen in my career. The traditional boundaries that once separated hardware, software, physics, packaging, and system behavior are rapidly disappearing. Verification engineers are no longer validating isolated digital logic — we’re increasingly responsible for ensuring correctness across highly interconnected, multi-domain systems.
Enabling Formal Verification at Scale: An Agentic AI-driven Approach to RTL Bring-up

Conference - Apr 28, 2026 by Nirmala Balakrishnan

This session describes a verification methodology transformation that enabled a design team to adopt formal verification techniques despite being completely new to formal flows. The team previously relied heavily on simulation-based verification without static analysis or formal methods, with limited personnel and expertise to write properties or deploy formal tools effectively.
Broadcom: Reining in the Complexity of DFT Verification

Conference - Apr 28, 2026 by Michael Batek

As semiconductor complexity grows unabated, featuring hundreds of physical core instances and multi-die architectures, validating critical Design for Test (DFT) structures has become exceedingly difficult. The practical size of physical blocks isn't keeping pace with design size, leading to a proliferation of components requiring verification across design generations. This session will introduce techniques and methodologies developed to address these challenges.
Advancing Simulation Performance with Siemens QDX on MSFT Cobalt Silicon

Conference - Apr 28, 2026 by Sandesh Putturaya

With increasing semiconductor complexity, achieving robust DFT verification demands both high-quality simulation and scalable performance. Microsoft has partnered with Siemens to integrate Questa One Sim into our verification flows, enabling significant improvements in simulation efficiency and accuracy across timing and non-timing test modes. By deploying QDX, we’ve achieved dramatic runtime reductions, cutting verification cycles from two weeks to just a few days.
OnSemi: Unified Verification Platform (VPlatform)

Conference - Apr 28, 2026 by Yijun Loh

VPlatform is a comprehensive verification platform built on the UVMF, standardizing verification processes across OnSemi's teams and business units. It establishes a unified verification flow ensuring consistent architecture, best practices, and seamless collaboration. VPlatform enables easy VIP integration across diverse products, creating a scalable verification infrastructure.
Connected Verification and Validation: The Seamless Link Between Simulation and Emulation

Conference - Apr 28, 2026 by Harry Foster

As semiconductor complexity continues to escalate with AI/ML SoCs and advanced architectures, the industry faces a critical challenge: first silicon success rates are declining while project schedules slip further behind. Traditional verification approaches can no longer keep pace with the demands of modern chip design. This panel explores how connected verification and validation solutions create seamless workflows between simulation and emulation to tackle challenges more effectively.
From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

Webinar - Apr 22, 2026 by Ronen Shoham

In this webinar we will demonstrate how the Questa One Agentic Toolkit - announced in February 2026 and built on the industry-leading Questa One verification solution - transforms verification from isolated applications into intelligently orchestrated workflows through purpose-built Agentic AI that autonomously reasons, plans, and executes strategies while keeping engineers in the loop with approval controls at critical decision points.
From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

Resource (Slides (.PDF)) - Apr 22, 2026 by Ronen Shoham

Join us to explore how this open, MCP-based architecture enables seamless integration with GitHub Copilot, Claude Code, Cursor, Cline, or Siemens Fuse, supports vendor-neutral AI models (OpenAI, Anthropic, NVIDIA Nemotron), and delivers autonomous RTL signoff that liberates engineers from repetitive tasks while preserving human oversight for trusted design closure available for deployment today.
Why DFT Verification Signoff Is the Hidden Risk Threatening Your Next Tapeout

Resource (Verification Horizons Blog) - Apr 14, 2026 by Jake Wiltgen

Today’s chips integrate billions of transistors, dozens of IP blocks, and deeply hierarchical architectures, all of which must not only function correctly, but must also be testable after manufacturing. Design for Test (DFT) verification is a critical sign-off benchmark ensuring your test strategy and implementation is viable once chips start coming back.
BUGGED OUT Podcast - Episode 4: Vladislav Palfy

Resource (Podcast) - Apr 13, 2026 by Harry Foster

In episode 4, Harry Foster talks with Vladislav Palfy, Director of Solutions Management at Siemens EDA, about why coverage closure has become one of the biggest bottlenecks in modern verification. Drawing on insights from his white paper, Questa One Unified Coverage Solution: Transforming Verification Through Intelligence .
BUGGED OUT Podcast

Podcast - Apr 13, 2026 by Harry Foster

Every chip has bugs — the real question is how fast you can find and fix them. BUGGED OUT is the bite-sized podcast where we shine a light on the art (and science) of functional verification.
PCI Express 8.0: Powering AI, Cloud, and HPC with Transformative Interconnect Technology

Resource (Verification Horizons Blog) - Apr 09, 2026 by Gyanaranjan Khuntia - Siemens EDA

We are living through a data revolution that’s fundamentally changing how we design and build technology. From the neural networks that power tomorrow’s autonomous vehicles to the massive computational clusters that train the next generation AI models, one truth has become crystal clear: the bottleneck is not just about processing power anymore—it’s how fast we can move data between components.
DVCon US Keynote: Why Verification Must Evolve in the Convergence Era

Resource (Verification Horizons Blog) - Mar 25, 2026 by Harry Foster

At DVCon US 2026, a keynote delivered by three speakers—Abhi Kolpekwar (Siemens EDA), Jean-Marie Brunet (Siemens EDA), and Alon Shtepel (Micron)—shared a simple but important message: Verification is no longer a scaling problem. It’s a systems problem. For years, the industry has successfully handled increasing design size. More transistors? Add more compute. More IP? Run more regressions. That model served us well.