| Session Title |
Abstract |
Slides |
Integrating the Value of Questa Design Solutions Into Your Continuous Integration (CI) Development Flow
- Walter Gude | Applications Engineering Consultant |
In this presentation, we will show how to automate the detection of hard-to-spot issues (e.g., CDC, FSM deadlock, combo loops, etc.) as early as possible in the design cycle with a continuous integration environment. In this flow, design quality is automatically checked at every code check-in and other scheduled intervals – which can reduce costs and drive predictable schedule execution. |
PDF  |
Continuous Integration (CI) / DevSecOps
- Marty Rowe | Sr. Applications Engineer |
Modern systems and products rely on complex microelectronic components now more than ever to monitor, control and process critical information. Due to their importance in the system or product, an exploit of these devices may result in a risk to personal safety, financial loss, exposure of personal information, and operation failure. Functional verification of microelectronic devices requires thorough methods and verifying that the ICs in the system are free of these exploits requires even more. Siemens' OneSpin trust and security tools and apps have technologies built upon world class formal engines and provide quantitative data verification results desired in emerging cybersecurity standards. In this presentation we will introduce apps that provide an automated assessment
platform, perform processor verification, and offer completeness checking to perform security verification in your IC. |
PDF |
Debugging RTL and UVM in Post-sim and Live-sim in the Visualizer Debug Environment
- Rich Edelman | Product Engineer |
The Visualizer Debug Environment is the debug framework for simulation, static, formal, emulation, prototyping, analog and more. Visualizer and the Questa QIS technology ensures the fastest simulation while logging and prevents mismatches between regression simulations and debug simulations. The automated temporal causality trace back (Time cone view) finds root cause fast. Biometric search can highlight values or sequences with color. Visualizer raises the debug abstraction using the Transaction viewer, the FSM view, the logic cone and the schematic viewer. Complex UVM testbench can be debugged easily in the wave window. UVM connectivity can be visualized with the UVM Schematic. Live simulation adds breakpoints, break-on-change, memory usage monitoring. |
PDF |
Questa Verification IQ: Boost verification predictability and efficiency
- Jonathan Stanley | Sr. Applications Engineer |
Big Data is transforming all industries, enabling them to innovate their products more rapidly and improve many aspects of our lives. EDA is powering these transformations. Verification needs to transform in-step, so we can predict which test to run next, the root cause of a failure, and what stimulus is required. In this session, you will learn how Siemens’s latest offering, Questa™ Verification IQ (VIQ), can help you accelerate coverage closure, better manage your test and compute resources, and provide overall faster verification turnaround times by using analytics, collaboration, and traceability. Specifically, VIQ is the next generation, data-driven verification solution that transforms the verification process using analytics, collaboration, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years. |
PDF |
Simple, Maintainable, Accessible, and Reusable Testplans
- Toanl Nquyen | Director, VeriSi Corporation |
Testplans are a necessary step in the verification process but can be cumbersome depending on the user’s development environment. Available software may not be compatible with testplan plug-ins, and frustrating idiosyncrasies can arise during XML export. The YAML format is very similar to XML but is much more accessible and maintainable. Direct creation is simple, and conversion to an XML testplan is reliable. This presentation discusses the benefits of using the YAML format as a base for testplan generation. |
PDF |
Third-Party IP Assurance Using AutoCheck
- Luke Wolff | CTO, VeriSi Corporation |
The use of Third-Party Intellectual Property (3PIP) in Aerospace and Defense (A&D) designs raises concerns about the level of trust that can be placed in 3PIP. In the absence of a full testbench with documentation what can be done to improve trust in 3PIP? Questa Formal AutoCheck provides an option for assessing designs with a low threshold for design comprehension. This presentation will explore the application of AutoFormal to 3PIP and provide examples of issues found in real 3PIP. |
PDF |
Revolutionizing Circuit Design: Unveiling the latest updates and roadmap of Questa Simulation Tools
- Moses Satyasekaran | Director, Simulation Product Line |
Discover how our cutting-edge Questa Simulation tools revolutionize the industry and deliver users' best product experience. During this session, we will unveil our latest product updates and discuss our exciting investments in the future of our product roadmap. Plus, you'll get a behind-the-scenes look at our strategic investments in the product, including our plans for expanding functionality, enhancing performance, and delivering even greater value to our users. |
PDF |
