Siemens EDA 2021 Functional Verification Webinar Series

Simulation & Debug

Questa Verification IQ: Boost verification predictability and efficiency with Big Data

In this session, you will learn how you can accelerate your coverage closure using VIQ’s unique predictive and prescriptive data analysis, maximizing your team's efficiency.

Introduction to SystemVerilog Assertions

In this session, you will learn the benefits of using SystemVerilog assertions including; when and where to use assertions, language structure and implementation code examples.

Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.

Leveraging Advancements in UPF 3.1 for Effective Design and Verification

In this webinar, we shall explore some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.

Low Power Considerations for Verification

Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.

I Didn’t Know Visualizer Could Do That

In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Lint, CDC & RDC

Continuous Integration (CI) driving efficient program execution

In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.

Questa Design Solutions as a Sleep Aid

In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.

CDC and RDC Assist: Applying machine learning to accelerate CDC analysis

In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.

Questa Lint vs Formal AutoCheck

In this session you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.

Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost.

‘The Dog Ate my RTL’ Doesn’t Work Anymore

In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

Introduction to Questa Lint and CDC for Designers

In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.

Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies

In this session you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised.

CDC Philosophy: The existential questions of constraints, waivers, and truth

In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly.

Improving Initial RTL Quality

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

Trouble: Three CDC Glitches That Only a Netlist Will See

This session will help you lower risks, development schedules and costs by identifying netlist CDC issues that are never caught with normal RTL CDC runs

A Methodology for Comprehensive CDC+RDC Analysis

This session will help you improve your development schedules and predictability by identifying the key functions and processes that must be deployed in a comprehensive CDC and RDC methodology.

Advance your Designs with Advances in CDC and RDC

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC that are important to leverage early and often in development to ensure working and error-free multi-clock and reset designs.

Formal Verification

Exploring the Multi-faceted Landscape of Formal Coverage

In this session, you will learn how to effectively utilize formal coverage metrics to enhance verification closure and understand the essence of formal coverage and its implications on design quality

Breaking the RISC-V Processor Customization Barrier with Formal Verification

In this session, we present an automated, customer proven flow from ISA level specifications of custom extensions to their exhaustive formal verification and demonstrate results on popular open-source cores.

Efficient Interconnect Formal Verification for Complex, Large-scale Designs

In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.

Formal and the Next Normal

In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.

Formal 101 - Fast, Scalable Formal Verification Made Easy

In this session, we will give an overview of how to apply basic abstractions, how to set up & optimize constraints, and where and how to leverage Data Independence & Non-Determinism.

Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs

In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.

Formal 101 – Data Independence and Non-Determinism Made Easy

In this session, we will show how with a little design knowledge and forethought on your part, you can leverage these two principles to cut down your formal analysis to a matter of minutes vs. hours.

Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy

In this session, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.

Formal 101 – Setting Up & Optimizing Constraints

In this session we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints themselves, your test plan and formal coverage plan, and the DUT behavior.

Formal 101 – Basic Abstraction Techniques

In this session we will teach about the types of DUT constructs that commonly cause trouble for the formal analysis, and how to apply time-tested techniques to safely abstract them away so that the formal verification run can rapidly reach closure.

Equivalence Checking for FPGA

In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.

IP Security: Keys to Early Identification of Security Vulnerabilities

In this session we will demonstrate early security verification on a small module of intellectual property (IP) intended for integration into an IC. Using Methodics IPLM by Perforce’s key technology for IP management and OneSpin 360™ formal verification tools, our technical experts will jointly perform the process recently released for public comment in the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard.

How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.

The ABC of Formal Verification

This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.

Verification IP

New Leader in Verification IP, Delivering First Silicon Success for Your Next SoC or 3DIC

In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.

Protocol and Memory Interface Verification in the Shrinking World of 3DIC

In this session, we take a look at how to scale your verification capability to match those designs, divide and conquer, and use the right abstractions to equip projects with high quality and faster time-to-market, and to equip design/verification engineers with scalable tools and solutions for verification.

Creating a Fast and Productive USB4 Verification Environment

This session walks through the step-by-step workflow to integrate Questa Verification IP (QVIP) – USB4 into a testbench. The workflow demonstrates a jump start guide on developing a complete working testbench using QVIP, thereby reducing the testbench development efforts, and also the efforts needed for integrating QVIP into an existing testbench.

A Guide to QVIP Workflow and Debug for PCIe®

In this session, you will learn the step-by-step workflow to integrate Questa Verification IP (QVIP) - PCIe® into a testbench including key strides which dramatically reduces the integration efforts from weeks down to few hours allowing Verification Engineers to be more productive during their verification cycle.

VIP Solutions for Protocol and Memory Verification

In this session, we'll provide the key attributes of the Verification IP and Memory Model products, and a high level summary of how they can be used to bring quality and time-to-market value to your project.

Functional Safety

Union of SoC Design & Functional Safety Flow

In this session, you will learn how Siemens’ safety verification tools and unique methodologies are easy to adopt, and how they accelerate each development phase.

Achieving High Defect Coverage for Safety Critical and High Reliability Designs

In this session you will gain an understanding of how Siemens EDA provides practices, methodologies and integrated tool flows that provides a path to reaching the required manufacturing test quality needed for designs targeted at critically safe and high reliability markets.

Validation of Complex Safety Architectures

This session explains the methodology and flow of how to perform an accurate safety analysis, followed by fault simulation on the SoC or IP with a combination of hardware and software safety mechanisms.

Optimizing a Fault Campaign for Complex Mixed-Signal Devices

In this session, you will learn details how to effectively set up and execute an ISO 26262 fault campaign for mixed signal designs and establishing an efficient fault injection workflow for analog and digital portions of the design.

Exploration into Safety Analysis Techniques That Optimize the Safety Workflow

In this session, you will gain an understanding of how Siemens EDA provides a methodology that results in achieving a single iteration around costly fault injection, resulting in a more predictable project schedule and an accelerated time-to-certification.

Aero/Defense

Aerospace and Defense Verification Tech Day

Join Siemens EDA as we share an engineering update on the methodologies, technologies, and solutions for the ASIC, FPGA, and systems verification challenges unique to today’s aerospace and defense industry. Design and verification engineers and managers serving the aerospace and defense industry won’t want to miss this deep dive into the future of digital verification.

Easy Test Writing with a Proxy-driven Testbench

In this session we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.

The Digital Twin: An Aerospace and Defense Revolution

This session will provide a look into a seamless and comprehensive Digital Thread for Defense and the immense value it brings.

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