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Streamlining Requirements Traceability using Questa Verification IQ Testplan Author
Webinar - May 28, 2025 by Nishtha NLN
In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with Application Lifecycle Management tools (such as Siemens Polarion and Jama Connect) to deliver a powerful, collaborative traceability solution that transforms your verification workflow.
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Solving the Semiconductor Verification Crisis: From Problem to Productivity
Webinar - May 21, 2025 by Harry Foster
In this webinar, you will learn more about the challenges that are currently being faced by the digital design and verification industry and the steps you can take to mitigate some of these challenges.
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Enhancing Defect Coverage in Design for Testability (DFT) with Functional Fault Grading
Webinar - May 07, 2025 by Ann Keffer
In this webinar, we will explore how functional fault grading enhances defect coverage. Attendees will learn the key advantages of integrating functional fault grading into DFT processes, specifically addressing faults untestable by scan tests.
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Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity
Webinar - Apr 30, 2025 by Kevin Ham
This session introduces Avery Verification IP for Ethernet 1.6T, Infiniband, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity. You will gain insights into the key challenges and innovations in Ethernet 1.6T, the latest high-speed Ethernet standard, and learn how Avery's Verification IP accelerates design validation with comprehensive protocol coverage, scalability, and advanced debugging capabilities.
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Securing your FPGA Design from RTL through to the Bitstream
Webinar - Apr 23, 2025 by Keerthi Devraj
This session will briefly introduce practical tools such as the Siemens Analyze Architecture and VerifySecure technologies, highlighting how they support the overall security strategy. In addition, we will introduce Bitwise (powered by Red Balloon Security) as a point-and-click assurance tool that delivers rapid security analysis and hardening of FPGA bitstreams.
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Faster Debug Using QuestaSim Interactive Coverage Analysis
Webinar - Apr 16, 2025 by Justin Royse
This session we will explore the power of debugging code and functional coverage while simulation is still running. Learn how interactive coverage analysis brings another dimension to RTL and SV/UMV debugging which can lead to significant productivity boost and faster design and testbench bring up.
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Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator
Webinar - Apr 03, 2025 by Mark Carey
This session will explore the powerful Smart Debug features within Siemens EDA’s Questa Verification IQ Regression Navigator - a next-generation, collaborative browser-based data-driven verification solution. Leveraging advanced machine learning technology, these features enable you to accelerate root cause analysis and reduce debug turnaround time.
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PCIe Gen7 Verification with Siemens Avery Verification IP
Webinar - Mar 26, 2025 by Zhihong Zeng
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks.
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Safety Analysis for Automotive Chips Based on ISO 26262
Webinar - Mar 12, 2025 by Jyothy M Jaganathan
In this webinar, we will be focusing on the usage of SafetyScope at various stages of a safety design cycle: architectural phase, RTL phase and post-synthesis phase. We will also demo showing initial FIT calculations as well as the ISO 26262 metrics, what if analysis and exploration to reach ASIL B safety.
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Faster Debug of Complex Testbenches using Visualizer
Webinar - Mar 05, 2025 by Erik Jessen
In this webinar, we will explore essential capabilities such as basic line stepping, dynamic variable monitoring, constraint debugging, and UVM topology visualization. In addition, you will learn how to effectively identify and resolve issues in complex testbenches, streamline workflows, and enhance overall verification efficiency.
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Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
Webinar - Feb 19, 2025 by Kevin Urish
Security and safety policies across various domains such as aerospace and defense, embedded security, and automotive safety have been updated to require an FPGA verification chain spanning from verified HDL source, extending throughout the FPGA implementation tool chain, and culminating with the FPGA bitstream. In this session, you will learn comprehensive solutions to tackle current and emerging requirements for FPGA designs.
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Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator
Webinar - Feb 12, 2025 by Mark Carey
In this webinar, we explore the powerful smart regression features of collaborative browser-based data-driven verification. You will then learn how to harness the full potential of Questa Verification IQ to boost efficiency and productivity in your verification efforts, take advantage of automating the detection of design differences and optimize regression time by maximizing compute resources.
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Streamlining FPU Verification with an Alternative to C-reference Model Approaches
Webinar - Feb 05, 2025 by Gerardo Nahum
In this webinar, you will be introduced to the Questa FPU application, explaining how it can quickly detect design inconsistencies and reduce verification time from months to days (based on an easy setup process). You will also learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation.
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An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262
Webinar - Jan 29, 2025 by Jyothy M Jaganathan
In this webinar, you will learn more about Siemens EDA functional safety concepts and tool flow. In addition, we will walk you through our closed-loop solution; from requirements gathering, FMEDA, safety analysis, fault injection and back to merging the results to generate the work products necessary for certification.
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Explore How to Protect Against Data Corruption with Formal Security Verification
Webinar - Jan 22, 2025 by Keerthi Devraj
In this webinar, you will learn about the importance of hardware security including; why robust hardware security is fundamental to all security applications, especially as hardware forms the backbone of critical systems and the implications of hardware breaches, which can lead to severe financial, reputational, and operational consequences.
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Unlocking the Power of QuestaSim and Visualizer Integration
Webinar - Jan 15, 2025 by Justin Royse
In this webinar, you will learn how you can get faster simulation runs, smaller simulation databases. We will also cover qrun which simplifies your scripting environment by bringing together compilation, optimization and elaboration into a single command and fewer switches. Then we will cover how you can get better coverage performance using our Next-Gen Coverage engine.
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Boost Your Verification Productivity with Questa Verification IQ
Webinar - Nov 21, 2024 by Mark Carey
In this webinar, you will learn how to implement a collaborative, plan-driven verification process, complemented by a requirement-driven process for complete traceability from requirements to implementation and verification results.
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Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications
Webinar - Oct 30, 2024 by Kamlesh Mulchandani
In this session, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.
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Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Webinar - Sep 11, 2024 by Nicolae Tusinschi
In this session, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge, providing user-friendly interfaces, significantly reducing verification environment setup time. Optimized for top-tier performance and scalability, Questa Formal VIP AMBA achieves high-efficiency with accurate protocol compliance.
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The Future of Multi-Die System Verification with UCIe
Webinar - Aug 21, 2024 by Justin Bunnell
In this session, you will be introduced to the UCIe protocol with a focus on the latest evolutions of the specification, followed by a deep dive into the key features of Siemens Avery UCIe Verification IP that enable efficient verification of multi-die systems. These include dynamic block-level and System-in-Package (SiP) level testbench creation, intelligent traffic generation, error injection, advanced debug features, and comprehensive performance monitoring.
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Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim
Webinar - Jul 24, 2024 by Fan Zhang
In this session, you will be provided with an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally, we'll delve into QEMU, the open-source system emulator, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow.
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Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning
Webinar - May 22, 2024 by Farhad Ahmed
In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.
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Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim
Webinar - Apr 16, 2024 by Rich Edelman
Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.
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Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Webinar - Mar 27, 2024 by Rick Koster
This session will describe a reliable formal-based method to manage Xs in GLS. It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator.
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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Webinar - Mar 14, 2024 by Atul Sharma
In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.