Browse all Seminars in Siemens Verification Academy

June 2026

Verification Academy Live Hudson
Verification Academy Live Jun 09, 2026 Joe Hupcey Seminar

May 2026

Verification Academy Live BRNO University of Technology
Verification Academy Live May 21, 2026 Joe Hupcey Seminar

February 2026

Verification Academy Live: El Segundo
Verification Academy Live Feb 24, 2026 Joe Hupcey Seminar

November 2025

MARLUG - 2025
Simulation Nov 19, 2025 Sunil Sahoo Seminar

February 2025

Verification Academy Live: El Segundo
Verification Academy Live Feb 06, 2025 Joe Hupcey Seminar

September 2024

MARLUG - 2024
FPGA Verification Sep 18, 2024 Austin Mam Seminar

October 2023

MARLUG - 2023
Machine Learning Oct 30, 2023 Harry Foster Seminar

March 2021

Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design
High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda Seminar

June 2017

Enterprise Ethernet PHY Verification
Verification IP Jun 13, 2017 Akshay Sarup Seminar
Need for Speed - PCIe® GEN4 Verification
Verification IP Jun 13, 2017 Akshay Sarup Seminar
Creating a Thorough Verification Environment in Less Than Two Days
Verification IP Jun 13, 2017 Jason Polychronopoulos Seminar
Trends and Requirements in High Speed Interface Verification
Verification IP Jun 13, 2017 Niraj Mathur Seminar
MIPI® CSI-2 TX Verification
Verification IP Jun 13, 2017 Ivan Ristic Seminar
Leveraging the latest DDR & Flash Memory Models
Verification IP Jun 13, 2017 Jason Polychronopoulos Seminar
USB 3.1 Verification Challenges
Verification IP Jun 13, 2017 Dinesh Tyagi Seminar
Conquering the New IP Economy
Planning, Measurement and Analysis Jun 13, 2017 Harry Foster Seminar

November 2016

System Level Debug & Analysis
Debug Nov 11, 2016 Gordon Allan Seminar
Enterprise Debug for Simulation and Formal
Debug Nov 11, 2016 Moses Satyasekaran Seminar

February 2011

SystemVerilog Concurrent Assertions
SystemVerilog Feb 25, 2011 Cliff Cummings Seminar

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

VA Live - Hudson, MA

Tuesday, June 9, 2026 | 9:00 AM - 5:00 PM EDT

This seminar empowers design engineers and verification teams with knowledge and tools for advanced AI automation and intelligent verification.

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

Browse all Seminars in Siemens Verification Academy

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