On-Demand Debug Webinar

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Now Available

Search Results

Filters
Reset All

Filters

Topic

Content Type

Audience

Tags

Show More

Show Less

6 Results

  • Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs

    Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing.

  • Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs

    In this session, you will learn design considerations for PCIe 5.0 and 6.0 design IP and how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs.

  • Verification of HPC Protocols and Memories

    In this technical session we focus on the advances in PCI Express generation 6 protocol, and on the Compute Express Link (CXL) protocol.

  • Verification of HPC Protocols and Memories

    To enable High Performance Compute (HPC) architectures goals, there are new interconnect protocols, memory solutions, and storage connectivity solutions at all levels of the datacenter, from chip through package, board, backplane, module, and rack to facility level. New solutions change the game for design and verification, and demand expertise and comprehensive support from EDA.

  • Part II: Verification of PCIe® IP

    In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.

  • Part I: Introduction to PCIe® Gen 6

    In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe® 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.