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77 Results

• Ensuring Robust Reset Integrity in Complex SoC Designs Through Advanced Reset Tree Checks

  Resource (Verification Horizons Blog) - Nov 19, 2024 by Reetika - Siemens EDA

  One of the foundational steps in the reset domain crossing (RDC) verification process is determining the structure of the reset tree within a system-on-chip (SoC) design. The reset tree is critical for tracking how reset signals propagate throughout the design, ensuring stable and predictable system operation. To construct this reset tree, engineers rely on static analysis techniques to examine the register transfer level (RTL) of the design and identify various reset signals.

• Effective Identification of Reset Tree Bugs to Mitigate RDC Issues

  Resource (Technical Paper) - Nov 15, 2024 by Reetika - Siemens EDA

  This paper discusses these advanced structural checks, explaining how they are crucial for identifying potential issues early and ensuring the integrity of SoC designs.

• Effective Identification of Reset Tree Bugs to Mitigate RDC Issues

  Paper - Nov 15, 2024 by Reetika - Siemens EDA

  This paper emphasizes the importance of advanced reset tree structural checks to identify potential design issues prior to conducting RDC analysis. By doing so, these checks can significantly conserve both the time and effort expended by designers throughout the overall RDC verification process. This paper advocates for early detection and correction of such issues, underlining how advanced reset tree checks can enhance the integrity and reliability of SoC designs.

• New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

  Resource (Slides) - Mar 14, 2024 by Atul Sharma

  In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

• New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

  Webinar - Mar 14, 2024 by Atul Sharma

  In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

• The Democratization of Digital Methodologies for AMS Verification

  Article - Jul 05, 2022 by Sumit Vishwakarma

  A mixed-signal design is a combination of tightly interlaced analog and digital circuitry. Next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern systems on chips (SoCs). There are two critical reasons for this trend.

• Estimating Power Dissipation of End-User Application on RTL

  Resource (Recording) - Mar 23, 2022 by

• Confidently Sign-off any Low-Power Designs without Consequences

  Resource (Technical Paper) - Mar 23, 2022 by

• Estimating Power Dissipation of End-User Application on RTL

  Resource (Slides) - Mar 23, 2022 by

• Path-based UPF Strategies Optimally Manage Power on your Designs

  Resource (Technical Paper) - Mar 23, 2022 by

• Sequential Logic Equivalence Checking

  Track - Jul 06, 2021 by Jin Hou

  In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.

• SLEC for Low Power Clock Gating

  Session - Jul 06, 2021 by Jin Hou

  In this session, you will how to use SLEC to verify that the design works the same with and without added low power clock gating logic.

• SLEC for Safety Mechanism

  Session - Jul 06, 2021 by Jin Hou

  In this session, you will learn how to use SLEC to verify that the design’s safety mechanism handles faults as required.

• Leveraging Advancements in UPF 3.1 for Effective Design and Verification

  Webinar - Jun 23, 2021 by Gabriel Chidolue

  In this session, you will learn about some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.

• Low Power Considerations for Verification

  Webinar - Apr 29, 2021 by Rick Koster

  Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.

• Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

  Webinar - Mar 31, 2021 by Progyna Khondkar

  This session distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.

• Bringing Reset and Power Domains Together – Confronting UPF Instrumentation

  Webinar - Mar 31, 2021 by Abdul Moyeen

  This session specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.

• Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

  Resource (Slides) - Mar 31, 2021 by Progyna Khondkar

  Top level primary IOs remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications multifold at RTL and gate-level simulations for them.

• Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

  Resource (Technical Paper) - Mar 31, 2021 by Progyna Khondkar

  This paper distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.

• Bringing Reset Domains and Power Domains Together - Confronting Issues Due to UPF Instrumentation

  Resource (Slides) - Mar 31, 2021 by Abdul Moyeen

  The Unified Power format (UPF) standard enables designers to add power intent for the design. For power management designers typically partition design into power domains. Interactions between these power domains are done through various power control logics like retention logic, isolation logic, level shifters, etc. Designers need to validate that the power control logic does not introduce new multi-clock and multi-reset issues into the design.

• Bringing Reset Domains and Power Domains Together - Confronting Issues Due to UPF Instrumentation

  Resource (Technical Paper) - Mar 31, 2021 by Abdul Moyeen

  This paper specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.

• Low Power Coverage: The Missing Piece in Dynamic Simulation

  Article - Jan 07, 2020 by Progyna Khondkar

• A New Approach to Low Power Verification - Power Aware Apps

  Resource (Technical Paper) - Aug 21, 2019 by Madhur Bhargava

  This paper demonstrates how Power Aware Apps can help in reporting, debugging and self-checking low power designs. We will also highlight how these apps will help offer an efficient way to significantly save verification effort and time.

• A New Approach to Low-Power Verification: Power Aware Apps

  Paper - Aug 21, 2019 by Madhur Bhargava

  The effective verification of low-power designs has been a challenge for many years now. The IEEE Std 1801-2015 Unified Power Format (UPF) standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs.

• Integrated Approach to Power Domain/Clock-Domain Crossing Checks

  Webinar - Jun 20, 2019 by Ashish Amonkar

  Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.