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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Resource (Slides Download) - Mar 14, 2024 by Atul Sharma
In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.
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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Webinar - Mar 14, 2024 by Atul Sharma
In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.
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The Democratization of Digital Methodologies for AMS Verification
Article - Jul 05, 2022 by Sumit Vishwakarma
A mixed-signal design is a combination of tightly interlaced analog and digital circuitry. Next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern systems on chips (SoCs). There are two critical reasons for this trend.
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Power Aware Verification
Track - May 23, 2022 by Erich Marschner
This track introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.
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Estimating Power Dissipation of End-User Application on RTL
Resource (Recording) - Mar 23, 2022 by
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Confidently Sign-off any Low-Power Designs without Consequences
Resource (Technical Paper) - Mar 23, 2022 by
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Estimating Power Dissipation of End-User Application on RTL
Resource (Slides Download) - Mar 23, 2022 by
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Path-based UPF Strategies Optimally Manage Power on your Designs
Resource (Technical Paper) - Mar 23, 2022 by
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Sequential Logic Equivalence Checking
Track - Jul 06, 2021 by Jin Hou
In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.
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SLEC for Low Power Clock Gating
Session - Jul 06, 2021 by Jin Hou
In this session, you will how to use SLEC to verify that the design works the same with and without added low power clock gating logic.
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SLEC for Safety Mechanism
Session - Jul 06, 2021 by Jin Hou
In this session, you will learn how to use SLEC to verify that the design’s safety mechanism handles faults as required.
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Leveraging Advancements in UPF 3.1 for Effective Design and Verification
Webinar - Jun 23, 2021 by Gabriel Chidolue
In this session, you will learn about some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.
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Low Power Considerations for Verification
Webinar - Apr 29, 2021 by Rick Koster
Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.
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Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Webinar - Mar 31, 2021 by Progyna Khondkar
This session distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.
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Bringing Reset and Power Domains Together – Confronting UPF Instrumentation
Webinar - Mar 31, 2021 by Abdul Moyeen
This session specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.
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Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Resource (Slides Download) - Mar 31, 2021 by Progyna Khondkar
Top level primary IOs remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications multifold at RTL and gate-level simulations for them.
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Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Resource (Technical Paper) - Mar 31, 2021 by Progyna Khondkar
This paper distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.
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Bringing Reset Domains and Power Domains Together - Confronting Issues Due to UPF Instrumentation
Resource (Slides Download) - Mar 31, 2021 by Abdul Moyeen
The Unified Power format (UPF) standard enables designers to add power intent for the design. For power management designers typically partition design into power domains. Interactions between these power domains are done through various power control logics like retention logic, isolation logic, level shifters, etc. Designers need to validate that the power control logic does not introduce new multi-clock and multi-reset issues into the design.
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Bringing Reset Domains and Power Domains Together - Confronting Issues Due to UPF Instrumentation
Resource (Technical Paper) - Mar 31, 2021 by Abdul Moyeen
This paper specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.
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Low Power Coverage: The Missing Piece in Dynamic Simulation
Article - Jan 07, 2020 by Progyna Khondkar
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A New Approach to Low-Power Verification - Power Aware Apps
Resource (Technical Paper) - Aug 21, 2019 by Madhur Bhargava
The effective verification of low-power designs has been a challenge for many years now. The IEEE Std 1801-2015 Unified Power Format (UPF) standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs.
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A New Approach to Low-Power Verification: Power Aware Apps
Paper - Aug 21, 2019 by Madhur Bhargava
The effective verification of low-power designs has been a challenge for many years now. The IEEE Std 1801-2015 Unified Power Format (UPF) standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs.
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Integrated Approach to Power Domain/Clock-Domain Crossing Checks
Webinar - Jun 20, 2019 by Ashish Amonkar
Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.
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Reusable UPF - Transitioning from RTL to Gate Level Verification
Resource (Technical Paper) - Jun 11, 2019 by
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Random Directed Low-Power Coverage Methodology - A Smart Approach to Power Aware Verification Closure
Resource (Technical Paper) - May 22, 2019 by Madhur Bhargava
With the advancement in the technology, low-power design and its verification is becoming more complex. Today’s chips have multiple power domains each having multiple operating power modes and dynamically changing voltage levels.