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A multi-dimensional view of formal verification coverage
Resource (Slides Download) - May 31, 2023 by Nicolae Tusinschi
In this session, you will learn more about formal coverage and verification coverage integration advantages.
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Questa Visualizer Adds Coverage Analysis to the Platform
Article - Sep 01, 2021 by Yara Esam - Siemens EDA
Questa Visualizer Debug is our high performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs.
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Digital Functional Verification for Safety-Critical Automotive Applications
Webinar - Jul 29, 2021 by Michael Bierl - Siemens EDA
In this session, you will be shown a coverage driven verification flow based on the Questa platform. You will also learn how a web-based platform helps to finalize the project successfully even in teams spread over multiple locations.
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Purging CXL Cache Coherency Dilemmas
Article - Mar 03, 2021 by Nikhil Jain, Gaurav Manocha - Siemens EDA
The massive growth in the production and consumption of data, particularly unstructured data, like images, digitized speech, and video, results in an enormous increase in accelerators' usage. The growing trend towards heterogeneous computing in the data center means that, increasingly, different processors and co-processors must work together efficiently, while sharing memory and utilizing caches for data sharing.
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Visualizer Coverage: Debug and Visualize All Your Coverage
Webinar - Nov 19, 2020 by Athira Panicker
In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.
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Increasing Functional Coverage by Automation for Zetta-Hz High Speed CDMA Transceiver
Article - Oct 26, 2020 by Karthik Bandaru, Priyanka Gharat, and Sastry Puranapanda - Silicon Interfaces®
The efforts to apply constrained randomization to create test cases is based on the developer or verification engineer’s perception of what test vectors are required and can easily lead to hidden bugs being overlooked. Traditionally, the coverage goals would have been reached by writing more test cases with unpredictable schedules, often impacting time-to-market goals. Functional coverage defines critical states and constrained randomization tests those states in unpredictable ways.
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Unraveling the Complexities of Functional Coverage - An Advanced Guide to Simplify Use Models
Resource (Technical Paper) - Aug 02, 2019 by Thomas Ellis
In this paper we will outline a set of guidelines for writing an unambiguous coverage model.
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Debugging Functional Coverage Models: Get the Most of Out of Your Cover Crosses
Resource (Technical Paper) - May 13, 2019 by Mennatallah Amer
Applying hole analysis on each cover cross independently can lead to misleading results and is sometimes prohibitive due to the sheer number of crosses. Additionally, we introduce a metric, hole effect, that is proportional to the coverage gains that would result upon resolving the highlighted hole. We evaluate our approach on a real processor’s data processing unit to validate its applicability and usefulness for debugging complex functional coverage models.
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Debugging Functional Coverage Models: Get the Most Out of Your Cover Crosses
Paper - May 13, 2019 by Mennatallah Amer
Functional coverage models have grown in complexity to account for the increasing demands of designs today. Traditional and even advanced analysis techniques have yet to evolve to provide the verification engineer with actionable insights on how to debug their functional coverage model. In this paper, we generalize advanced hole analysis techniques to be able to get the most out of cover groups containing multiple cover crosses.
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Using Automation to Close the Loop Between Functional Requirements and their Verification
Webinar - Aug 10, 2018 by Brian Craw
This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.
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Using Automation to Close the Loop Between Functional Requirements and their Verification
Resource (Slides Download) - Aug 10, 2018 by Brian Craw
This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.
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Register-Level Functional Coverage
Chapter - Mar 18, 2018 by Verification Methodology Team
The UVM supports the collection of functional coverage based on register state in three ways:
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Accelerating Coverage Closure
Resource (Slides Download) - Oct 17, 2017 by Mark Handover
In this session, you will learn why Coverage Closure ranks at the top of FPGA verification challenges and how you can improve coverage quality.
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Coverage & Plan-Driven Verification for FPGAs
Webinar - Sep 06, 2017 by Brian Mathewson
This session explores how to ensure that debug and verification is done in the most effective place by using block benches, chip benches, formal tools, and lab test appropriately.
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Formal Coverage
Track - Aug 21, 2017 by Mark Eslinger
Formal coverage is a hot topic these days. Simulation has a number of metrics for helping determine when verification is done. These include code coverage, assertions coverage, transaction coverage, and functional coverage to name a few.
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Formal Coverage vs. Simulation Coverage
Session - Aug 21, 2017 by Mark Eslinger
This session will explore the various aspects of simulation coverage metrics.
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Formal Coverage vs. Simulation Coverage
Resource (Slides Download) - Aug 21, 2017 by Mark Eslinger
This session will explore the various aspects of simulation coverage metrics.
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A New Stimulus Model for CPU Instruction Sets
Article - Nov 01, 2015 by Staffan Berg, Mike Andrews - Siemens EDA
Verifying that a specific implementation of a processor is fully compliant with the specification is a difficult task. Due to the very large total stimuli space it is difficult, if not impossible, to ensure that every architectural and micro-architectural feature has been exercised. Typical approaches involve collecting large test-suites of real SW, as well as using program generators based on constrained- random generation of instruction streams, but there are drawbacks to each.
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Verification Methodology Cookbooks
Cookbook - Jun 29, 2015 by Verification Methodology Team
Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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New School Coverage Closure
Webinar - May 29, 2015 by Mark Eslinger
In this session, you will learn a new school formal verification method which automates the job of focusing coverage closure efforts.
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Coverage Cookbook - Japanese Release
Resource (Cookbook Japanese Translation) - Jan 14, 2015 by
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Questa Coverage Closure
Demo - Oct 22, 2014 by Thomas Ellis
In this demo, you will learn a few of the key features of the Questa Verification Platform as applies to the process of coverage closure.
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Functional Coverage with Covergroups
Session - Aug 06, 2014 by Ray Salemi
In this session you will learn how to create a covergroup.
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Verification Cookbook Glossary
Chapter - Mar 31, 2014 by Verification Methodology Team
This page is an index to the glossary of various terms defined and used in the Cookbook.
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Register Model Coverage
Chapter - Mar 31, 2014 by Verification Methodology Team
Which covergroups get built within a register block object or a register object is determined by a local variable called m_has_cover.