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Simulating AMD’s next-gen Versal Adaptive SoC devices using QuestaSim

Wednesday, July 24th - 8:00 AM US/Pacific

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64 Results

  • Coverage Closure Acceleration Using Collaborative Verification IQ Tool

    In this session you will learn that ever-increasing design complexity and shortening design-to-market has demanded faster and more accurate functional verification.

  • Enhanced Randomization and Functional Coverage – Make Better VHDL Testbenches

    In this session you will learn that UVVM’s advanced and optimized randomization and functional coverage was developed in cooperation with ESA (European Space Agency).

  • A multi-dimensional view of formal verification coverage

    In this session, you will learn more about formal coverage and verification coverage integration advantages.

  • Questa Visualizer Adds Coverage Analysis to the Platform

    Questa Visualizer Debug is our high performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs.

  • Digital Functional Verification for Safety-Critical Automotive Applications

    In this session, you will be shown a coverage driven verification flow based on the Questa platform. You will also learn how a web-based platform helps to finalize the project successfully even in teams spread over multiple locations.

  • Purging CXL Cache Coherency Dilemmas

    The massive growth in the production and consumption of data, particularly unstructured data, like images, digitized speech, and video, results in an enormous increase in accelerators' usage. The growing trend towards heterogeneous computing in the data center means that, increasingly, different processors and co-processors must work together efficiently, while sharing memory and utilizing caches for data sharing.

  • Visualizer Coverage: Debug and Visualize All Your Coverage

    In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.

  • Increasing Functional Coverage by Automation for Zetta-Hz High Speed CDMA Transceiver

    The efforts to apply constrained randomization to create test cases is based on the developer or verification engineer’s perception of what test vectors are required and can easily lead to hidden bugs being overlooked. Traditionally, the coverage goals would have been reached by writing more test cases with unpredictable schedules, often impacting time-to-market goals. Functional coverage defines critical states and constrained randomization tests those states in unpredictable ways.

  • Exercising State Machines with Command Sequences

    Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design.

  • Unraveling the Complexities of Functional Coverage - An Advanced Guide to Simplify Use Models

    In this paper we will outline a set of guidelines for writing an unambiguous coverage model.

  • Debugging Functional Coverage Models: Get the Most of Out of Your Cover Crosses

    Applying hole analysis on each cover cross independently can lead to misleading results and is sometimes prohibitive due to the sheer number of crosses. Additionally, we introduce a metric, hole effect, that is proportional to the coverage gains that would result upon resolving the highlighted hole. We evaluate our approach on a real processor’s data processing unit to validate its applicability and usefulness for debugging complex functional coverage models.

  • Debugging Functional Coverage Models: Get the Most Out of Your Cover Crosses

    Functional coverage models have grown in complexity to account for the increasing demands of designs today. Traditional and even advanced analysis techniques have yet to evolve to provide the verification engineer with actionable insights on how to debug their functional coverage model. In this paper, we generalize advanced hole analysis techniques to be able to get the most out of cover groups containing multiple cover crosses.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.

  • Register-Level Functional Coverage

    The UVM supports the collection of functional coverage based on register state in three ways:

  • Accelerating Coverage Closure

    In this session, you will learn why Coverage Closure ranks at the top of FPGA verification challenges and how you can improve coverage quality.

  • Coverage & Plan-Driven Verification for FPGAs

    This session explores how to ensure that debug and verification is done in the most effective place by using block benches, chip benches, formal tools, and lab test appropriately.

  • Formal Coverage

    Formal coverage is a hot topic these days. Simulation has a number of metrics for helping determine when verification is done. These include code coverage, assertions coverage, transaction coverage, and functional coverage to name a few.

  • Formal Coverage vs. Simulation Coverage

    This session will explore the various aspects of simulation coverage metrics.

  • Formal Coverage vs. Simulation Coverage

    This session will explore the various aspects of simulation coverage metrics.

  • A New Stimulus Model for CPU Instruction Sets

    Verifying that a specific implementation of a processor is fully compliant with the specification is a difficult task. Due to the very large total stimuli space it is difficult, if not impossible, to ensure that every architectural and micro-architectural feature has been exercised. Typical approaches involve collecting large test-suites of real SW, as well as using program generators based on constrained- random generation of instruction streams, but there are drawbacks to each.

  • Verification Methodology Cookbooks

    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

  • New School Coverage Closure

    In this session, you will learn a new school formal verification method which automates the job of focusing coverage closure efforts.

  • Coverage Cookbook - Japanese Release

  • Questa Coverage Closure

    In this demo, you will learn a few of the key features of the Questa Verification Platform as applies to the process of coverage closure.