Search Results

Advanced Search

2079 Results

Testbench Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session examines testbench enhancements and the value they deliver.
RTL Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session examines the RTL enhancements in VHDL-2008 and the value they deliver.
Operator Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session will discuss the value of the many new enhancements to the VHDL-2008 operators.
Package Type Enhancements

Session - Jan 18, 2013 by Jim Lewis

The session explores the new packages and modifications to the packages as well as the value these updates deliver.
Fixed Point Package

Session - Jan 18, 2013 by Jim Lewis

This session will explain the details of the new fixed point package.
Floating Point Package

Session - Jan 18, 2013 by Jim Lewis

This session will explain the details of the new floating point package.
VHDL-2008 Why It Matters

Track - Jan 17, 2013 by Jim Lewis

VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages.
Effectively Modeling and Analyzing Coverage

Webinar - Nov 15, 2012 by Tom Fitzpatrick

In this session, we will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret.
ST-Ericsson Speeds Time to Functional Verification Closure with Questa

Article - Oct 01, 2012 by Rachida El IDRISSI - ST-Ericsson

Functional verification is one of the most critical steps in the IC development cycle. As complexity increases, along with the associated cost of fixing late-stage functional defects, manufacturers including ST-Ericsson are putting additional effort into the up-front verification process.
The Top Five Formal Verification Applications

Article - Oct 01, 2012 by Roger Sabbagh - Siemens EDA

It's no secret. Silicon development teams are increasingly adopting formal verification to complement their verification flow in key areas. Formal verification statically analyzes a design's behavior with respect to a given set of properties.
Three Steps to Unified SoC Design and Verification

Article - Oct 01, 2012 by Mark Peryer

Developing a SoC is a risky business in terms of getting it right considering the technical complexity involved, managing the mixture of hardware and software design disciplines, and finding an optimal trade-off between design performance and power. One way to reduce these risks is to use a design and verification flow that is scalable enough to handle the complexity and is flexible enough to explore architectural alternatives early in the design cycle before implementation starts.
Evolution of UPF: Getting Better All the Time

Article - Oct 01, 2012 by Erich Marschner

This article gives a high-level overview of the concepts and capabilities that UPF provides and how those concepts and capabilities have evolved over the past few years. It also gives a preview of what is coming in the next version of UPF.
Improving Analog/Mixed-Signal Verification Productivity

Article - Oct 01, 2012 by Ahmed Eisawy

Nearly all of today's chips contain Analog/Mixed-Signal circuits. Although these often constitute only 25% of the total die, they may be 100% of the product differentiation and also, unfortunately, 80% of the problems in actually getting the chip to market in a cost effective and timely way.
VHDL-2008: Why It Matters

Article - Oct 01, 2012 by Jim Lewis

This article overviews the changes and the value they bring to your design process. Topics are categorized into three major sections: testbench, RTL, and packages/operators.
Verification Horizons - Volume 8, Issue 3

Resource (Verification Horizons Archive) - Oct 01, 2012 by Tom Fitzpatrick

"For verification, productivity really comes down to being able to reliably determine if your chip will run correctly as efficiently as possible.”
UVM 1.1c Class Reference

Resource (Reference Documentation) - Sep 19, 2012 by

v1.1c The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
More UVM Registers

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to implement registers and score-boarding at the register layer.
Protocol Layering

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.
Introduction to UVM Registers

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will be introduced to the Register Layer and how to get started writing tests and sequences and checking results at the register layer.
C-Based Stimulus for UVM

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn more about a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents.
UVM Debug

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this Verification Cookbook session, you will learn how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.
Scoreboards and Results Predictors in UVM

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.
OVM to UVM Migration

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session you will be introduced to a step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.
Customization in UVM

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT and how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.
Improving FPGA Debugging with Assertions

Article - Sep 10, 2012 by Harry Foster

Here’s one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics.