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Verification Horizons - Volume 9, Issue 1

Resource (Verification Horizons Archive) - Feb 01, 2013 by Tom Fitzpatrick

"As verification engineers, we have to be able to forecast the accurate completion of our projects and also be able to cope with problems that may occur. Unfortunately, there are severe consequences when we get it wrong.”
Improve AMS Verification Quality

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces a tool can be adapted in existing design flows supporting the available methodologies with little or no impact on the design flow.
Extend Structured Formal Verification to AMS

Session - Jan 25, 2013 by Ahmed Eisawy

This sessions defines the necessary extensions to the Digital Structured Formal Verification to the Mixed-Signal environment.
Extend Power-Aware Verification to AMS

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the concept of Power-Aware verification, why it’s needed in a Digital domain and how it can be used in an AMS design.
Analog Aspects in AMS

Session - Jan 25, 2013 by Ahmed Eisawy

This session covers the main aspects that affect the Quality of an Analog design and introduces the possible means to address those areas.
Overview to Improve AMS Quality

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the challenges in improving Mixed-Signal Verification Quality.
AMS Design Configuration Schemes

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces a tool can be adapted in various topologies supporting the available methodologies with little or no impact on the design flow.
Mixing Languages

Session - Jan 25, 2013 by Ahmed Eisawy

This session defines the language choices available in a Mixed-Signal design structure and how each choice impacts the performance and quality of the process.
Design Topologies

Session - Jan 25, 2013 by Ahmed Eisawy

This session covers the 2 main design topologies: Analog-Centric Mixed-Signal Designs and Digital-Centric Mixed-Signal Designs
Design Methodologies

Session - Jan 25, 2013 by Ahmed Eisawy

This session covers the 2 main flows used in Mixed-Signal design environments: Bottom-Up Design Flow and Top-Down Design Flow.
Analog/Mixed-Signal Domain

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the definition for Mixed-Signal domain and addresses the three main areas for AMS design: functionality, robustness and reliability.
Overview to AMS Configuration

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the opposing powers in Design Methodologies and the concept of Mixed-Signal design environments. Challenges and techniques will also be covered.
Improve AMS Verification Performance

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces a tool that will help verify complex Mixed-Signal designs to reach the goal of successful first tape-out.
AMS Modeling Guidance

Session - Jan 25, 2013 by Ahmed Eisawy

This session attempts to offer some general guidelines in developing Models for the various Analog and Mixed-Signal domain.
Modeling Abstraction

Session - Jan 25, 2013 by Ahmed Eisawy

This session defines the language choices available in a Mixed-Signal design structure and how each choice impacts the performance and quality of the results.
AMS Engines

Session - Jan 25, 2013 by Ahmed Eisawy

This session covers the 2 main simulator technologies used in Mixed-Signal verification: AMS Simulation and Analog/Digital Co-Simulation.
Overview to Improve AMS Performance

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the challenges in Mixed-Signal verification performance.
VHDL-2008 Overview

Session - Jan 18, 2013 by Jim Lewis

This session is a brief overview of all the VHDL-2008 improvements.
Testbench Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session examines testbench enhancements and the value they deliver.
RTL Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session examines the RTL enhancements in VHDL-2008 and the value they deliver.
Operator Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session will discuss the value of the many new enhancements to the VHDL-2008 operators.
Package Type Enhancements

Session - Jan 18, 2013 by Jim Lewis

The session explores the new packages and modifications to the packages as well as the value these updates deliver.
Fixed Point Package

Session - Jan 18, 2013 by Jim Lewis

This session will explain the details of the new fixed point package.
Floating Point Package

Session - Jan 18, 2013 by Jim Lewis

This session will explain the details of the new floating point package.
VHDL-2008 Why It Matters

Track - Jan 17, 2013 by Jim Lewis

VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages.