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Making it Easy to Deploy the UVM

Article - Jun 01, 2013 by Dr. Christoph Sühnel - Frobas GmbH

This article describes an UVM approach reducing testbench implementation effort, guaranteeing an early success and streamlining the processing of the test results. Depending on the number of functional interfaces and the design complexity up to 6 weeks of implementation effort or even more can be saved. A runnable UVM testbench will be handed over to the verification team at the very beginning of the project.
NoC Generic Scoreboard VIP

Article - Jun 01, 2013 by François Cerisier, Mathieu Maisonneuve - TVS

The increase of SoC complexity with more cores, IPs and other subsystems has led SoC architects to demand more from the main interconnect or network-on-chip (NoC), which is thus becoming a key component of the system.
Flexible UVM Components: Configuring Bus Functional Models

Article - Jun 01, 2013 by Gunther Clasen - Ensilica

This article shows a way to write BFMs in such a way that they can be configured like any other UVM component using uvm_config_db. This allows a uniform configuration approach and eases reuse. All code examples use UVM, but work equally with the set_config_*() functions in OVM.
Monitors, Monitors Everywhere – Who Is Monitoring the Monitors

Article - Jun 01, 2013 by Rich Edelman

The reader of this article should be interested in predicting or monitoring the behavior of his hardware. This article will review phase-level monitoring, transaction-level monitoring, general monitoring, in-order and out-of-order transaction-level monitors, A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated. Under certain AXI usages, problems arise.
The Need for Speed: Understanding Design Factors that Make Multi-core Parallel Simulations Efficient

Article - Jun 01, 2013 by Shobana Sudhakar

The intent of this article is to educate customers and guide them to understand what makes a design multicore friendly. This can help customers write designs and testbenches to be more suited for parallel simulations. Cases of success and failures of QuestaSim MC2 deployments and the lessons learned from them form the basis of our analysis and substantiate our suggestions in this article.
An Enhanced UPF Example

Session - May 31, 2013 by Chuck Seeley

This session presents an extended example illustrating the usage of the UPF 2.0 features of IEEE Std 1801 UPF for specification of the power management architecture for a simple design.
Using Supply Sets

Session - Apr 29, 2013 by Chuck Seeley

This session presents the UPF 2.0 concept of a “supply set” and the related commands and options used for defining and using supply sets.
UPF 2.0 Enhancements

Session - Apr 08, 2013 by Chuck Seeley

This session presents UPF 2.0 commands and options that improve usability and provide greater flexibility.
A Simple UPF Example

Session - Apr 08, 2013 by Chuck Seeley

This session presents an extended example illustrating the usage of the UPF 1.0 subset.
Getting Started with UPF

Session - Apr 08, 2013 by Erich Marschner

This session presents the core commands and options in UPF 1.0 subset.
Introduction to Power Aware Verification

Session - Apr 08, 2013 by Erich Marschner

This session introduces the IEEE Std 1801 Unified Power Format (UPF).
Overview of UPF

Session - Apr 08, 2013 by Erich Marschner

This session gives a quick, high-level overview of the evolution of the UPF standard.
Power Aware Verification

Track - Apr 05, 2013 by Erich Marschner

This track introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.
Functional Verification Study - 2012

Session - Apr 01, 2013 by Harry Foster

In this session, Harry Foster highlights the key findings from the 2012 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
UVM 1.1d Class Reference

Resource (Reference Documentation) - Mar 07, 2013 by

v1.1d The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
Using Formal Analysis to Block and Tackle

Article - Feb 25, 2013 by Paul B. Egan - Rockwell Automation

This article will explain how we applied formal analysis at the block level, extended this to full chip and describe how we significantly reduced verification time at both the block and chip level. Just like a block and tackle provides a mechanical advantage, the formal connectivity flow provides a verification advantage
Bringing Verification and Validation under One Umbrella

Article - Feb 25, 2013 by Hans Van Der Schoot

The standard practice of developing RTL verification and validation platforms as separate flows, forgoes large opportunities to improve productivity and quality that could be gained through the sharing of modules and methods between the two. Bringing these two flows together would save an immense amount of duplicate effort and time while reducing the introduction of errors, because less code needs to be developed and maintained.
System Level Code Coverage using Vista Architect and SystemC

Article - Feb 25, 2013 by Ken P. McCarty - Siemens EDA

SoC are constantly becoming more and more complex forcing design teams to eke out as much performance as possible just to stay competitive. Design teams need to get it right from the start and can't wait until it's built to find out how it truly performs. This is where System Level Modeling and SystemC/TLM shine.
The Evolution of UPF: What’s Next?

Article - Feb 25, 2013 by Erich Marschner

Usage of the Unified Power Format (UPF) is growing rapidly as low power design and verification becomes increasingly necessary. In parallel, the UPF standard has continued to evolve. A previous article1 described and compared the initial UPF standard, defined by Accellera, and the more recent IEEE 1801-2009 UPF standard, also known as UPF 2.0. The IEEE definition of UPF is the current version of the standard, at least for now, but that is about to change.
Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features

Article - Feb 25, 2013 by Ajeetha Kumari, Srinivasan Venkataramanan - CVC Pvt. Ltd.

SystemVerilog has become the most widely deployed Verification language over the last several years. Starting with the early Accellera release of 3.1a standard, the first IEEE 1800-2005 standard fueled the widespread adoption in tools and user base. Since 2005 there is no look-back to this "all encompassing" standard that tries to satisfy and do more for RTL Designers and Verification engineers alike.
SVA in a UVM Class-based Environment

Article - Feb 25, 2013 by Ben Cohen

This article demonstrates how SVA complements a UVM class-based environment. It also demonstrates how the UVM severity levels can be used in all SVA action blocks instead of the SystemVerilog native severity levels.
The Formal Verification of Design Constraints

Article - Feb 25, 2013 by Ajay Daga - FishTail Design Automation

There are two approaches to the verification of design constraints: formal verification and structural analysis. Structural analysis refers to the type of analysis performed by a static timing tool where timing paths either exist or not based on constant settings and constant propagation.
OVM to UVM Migration, or There and Back Again: A Consultant’s Tale

Article - Feb 25, 2013 by Mark Litterick - Verilab GmbH

This article presents an interesting OVM to UVM migration story where we successfully translated a whole family of verification components from OVM 2.1.2 to UVM, assessed the impact, and then reworked the original OVM code, which was still live in a series of ongoing derivative projects, to make the ongoing translations totally automatic and part of the project release mechanism.
Monitors, Monitors Everywhere – Who Is Monitoring the Monitors

Resource (Paper (.PDF)) - Feb 07, 2013 by Rich Edelman

In a verification environment the task of a monitor is to monitor activity on a set of DUT pins. This could be as simple as looking at READ/WRITE pins or as complex as a complete protocol bus, such as AXI or PCIe. In a very simple case a monitor can be looking at a pin or a set of pins and generating an event or raising a flag every time there is a change in signal values. The flag or event can trigger a scoreboard or coverage collector to perform an activity.
Monitors, Monitors Everywhere – Who Is Monitoring the Monitors

Paper - Feb 07, 2013 by Rich Edelman

This paper will review phase-level monitoring, transaction-level monitoring, and general monitoring. In-order and out-of-order transaction-level monitors and UVM constructs for single and multiple port monitors will be demonstrated, including discussion about simple function implementations versus FIFO and threaded implementations. A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated.