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Use_models_tb_build_tbx_uvm.tgz

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Use_models_unidirectional.tgz

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Uvm_Abstract-concrete.tgz

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Uvm_generation_seq_persistence.tgz

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Uvm_generation_seq_poly.tgz

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Uvm_generation_seq_rand.tgz

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Uvm_interrupts_prioritised.tgz

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Uvm_mem_example.tgz

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Verification Horizons - Volume 9, Issue 3

Resource (Verification Horizons Archive) - Oct 01, 2013 by Tom Fitzpatrick

"David is an Eagle Scout and our troop’s Senior Patrol Leader... I’m the Scoutmaster... What that really means is that David and I have to work together to make sure that the troop functions well as a unit...”
Software-Driven Testing of AXI Bus in a Dual Core ARM® System

Article - Oct 01, 2013 by Mark Olen

Here we present an architecture for verifying proper operation and performance of a complex AXI bus fabric in a dual-core ARM® processor system using a combination of SystemVerilog and C software-driven test techniques.
Caching in on Analysis

Article - Oct 01, 2013 by Mark Peryer

The on-chip bus interconnect has become a critical subsystem of a System On a Chip (SoC). Its function is to route data between different parts of the system at a rate that allows the system to meet its performance goals.
Simulation + Emulation = Verification Success

Article - Oct 01, 2013 by Lanfranco Salinari, Alberto Allara, and Alessandro Daolio - STMicroelectronics

STMicroelectronics is one of the world's largest semiconductor companies with net revenues of US$ 8.49 billion in 2012. Offering one of the industry's broadest product portfolios, ST serves customers across the spectrum of electronics applications with innovative semiconductor solutions.
Life Isn't Fair, So Use Formal

Article - Oct 01, 2013 by Roger Sabbagh - Siemens EDA

Most things in life are not evenly distributed. Consider for example, the sun and the rain. The city of Portland, Oregon gets much more than its fair share of rainy days per year at 164 on average, while in Yuma, Arizona, 90% of all daylight hours are sunny 1 . Or, how about life as an adolescent?
AMS Verification for High Reliability and Safety Critical Applications

Article - Oct 01, 2013 by Martin Vlach

Today, very high expectations are placed on electronic systems in terms of functional safety and reliability. Users expect their planes, automobiles, and pacemakers to work perfectly, and keep on working for years. A reboot of a smartphone is annoying, but rebooting the airplane or car electronics while underway could be catastrophic, and a glitch in an implanted medical device could be life threatening.
Assertions Instead of FSMs/logic for Scoreboarding and Verification

Article - Oct 01, 2013 by Ben Cohen

Monitors, scoreboards, and verification logic are typically implemented using FSMs, logic, and tasks. With UVM, this logic is hosted in classes. This article demonstrates another option of implementing some monitors and scoreboards using SVA assertions hosted in SV interfaces.
Basic UVM Code Examples

Resource (Tarball) - Oct 01, 2013 by Verification Methodology Team
UVM Connect Guide

Resource (Reference Documentation) - Sep 08, 2013 by Adam Erickson
UVM Register Model CSV Example

Resource (Reference Documentation) - Aug 15, 2013 by Tom Fitzpatrick

The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication.
Automate UVM Register Models

Webinar - Aug 15, 2013 by Tom Fitzpatrick

In this session, you will be introduced to the UVM Register Assistant that will show how to generate correct-by-construction register models and tests from a register specification.
Verification Horizons - Volume 9, Issue 2

Resource (Verification Horizons Archive) - Jun 01, 2013 by Tom Fitzpatrick

"Building a theater set is not unlike what we do as verification engineers. It involves modeling the “real world,” often at a higher level of abstraction, and it has hard deadlines.”
Interviewing a Verification Engineer

Article - Jun 01, 2013 by Akiva Michelson - Ace Verification

A key challenge today is choosing the right staff for achieving excellent verification results. Indeed, the defining moment for most projects is when the staff is selected, since the right combination of skills and personality can lead to outstanding technical outcomes (while the wrong combination can lead to disaster). Verification engineers differ significantly from other engineers in terms of skill sets required for success.
Non-invasive Software Verification Using Vista Virtual Platforms

Article - Jun 01, 2013 by Alex Rozenman, Vladimir Pilko, Nilay Mitash - Siemens EDA

With the SoCs now supporting Multi-Core processors, complex ASICs and combinations that include systems on a board, SoC implementations now become an ever-growing challenge for software development. Software development has to be supported not only by the inclusion of an RTOS, but, many SoC providers now have to leverage upon the Bare-Metal concept to achieve the necessary demands of today's SoCs.
QVM: Enabling Organized, Predictable, and Faster Verification Closure

Article - Jun 01, 2013 by Pradeep Salla

Until recently, the semiconductor industry religiously followed Moore's Law by doubling the number of transistors on a given die approximately every two years. This predictable growth allowed ecosystem partners to plan and deal with rising demands on tools, flows and methodologies. Then came the mobile revolution, which opened up new markets and further shifted the industry's focus to consumers.
Verifying High Speed Peripheral IPs

Article - Jun 01, 2013 by Sreekanth Ravindran, Chakravarthi M.G. - Mobiveil

In this article, Silicon IP and platform enabled solution provider Mobiveil shares its story of verifying high speed bus protocol standards like PCI Express and Serial RapidIO, including what considerations are required when verifying high speed designs.
Confidence in the Face of the Unknown: X-state Verification

Article - Jun 01, 2013 by Kaowen Liu - MediaTek Inc., Roger Sabbagh - Siemens EDA

Unknown signal values in simulation are represented as X-state logic levels, while the same X-states are interpreted as don't care values by synthesis. This can result in the hazardous situation where silicon behaves differently than what was observed in simulation. Although the general awareness of X-state issues among designers is good, gotchas remain a risk that traditional verification flows are not well equipped to guard against.