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Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
Resource (Slides (.PDF)) - Feb 19, 2025 by Kevin Urish
In this session, you will learn comprehensive solutions to tackle current and emerging requirements for FPGA designs.
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Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
Webinar - Feb 19, 2025 by Kevin Urish
Security and safety policies across various domains such as aerospace and defense, embedded security, and automotive safety have been updated to require an FPGA verification chain spanning from verified HDL source, extending throughout the FPGA implementation tool chain, and culminating with the FPGA bitstream. In this session, you will learn comprehensive solutions to tackle current and emerging requirements for FPGA designs.
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IC/ASIC Functional Verification Trend Report - 2024
Paper - Feb 17, 2025 by Harry Foster
The 2024 Wilson Research Group Functional Verification Study provides an in-depth analysis of trends in IC/ASIC functional verification. The findings reveal the mounting challenges of verifying increasingly complex designs, driven by the rise of SoC-class architectures, security, safter-critical requirements and asynchronous clock domains. Alarmingly, first-silicon success rates have declined to their lowest level in two decades, with only 14 percent of projects achieving this milestone.
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FPGA Functional Verification Trend Report - 2024
Paper - Feb 17, 2025 by Harry Foster
The 2024 Wilson Research Group Functional Verification Study provides a detailed examination of trends in FPGA functional verification. The findings highlight the growing complexity of FPGA designs and the corresponding increase in verification challenges. While FPGAs continue to offer advantages such as flexibility and cost-effectiveness, their evolving use in applications like AI acceleration and system-on-chip (SoC) designs necessitates advanced verification methodologies.
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2024 Siemens EDA and Wilson Research Group Functional Verification Study: 7-Part Video Series
Track - Feb 17, 2025 by Harry Foster
The complexity of semiconductor design continues to grow, making functional verification a critical challenge. This 7-part video series presents key findings from the latest Siemens EDA and Wilson Research Group Functional Verification Study , covering both ASIC and FPGA trends.
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Introduction and Study Background
Session - Feb 17, 2025 by Harry Foster
Get an overview of the Siemens EDA and Wilson Research Group study, including its methodology, industry scope, and the critical questions it addresses about ASIC and FPGA verification trends.
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IC/ASIC Functional Verification Trend Report - 2024
Resource (Paper (.PDF)) - Feb 17, 2025 by Harry Foster
This report examines the trends in functional verification for integrated circuits (ICs) and application-specific integrated circuits (ASICs) as identified in the 2024 Wilson Research Group study.
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FPGA Functional Verification Trend Report - 2024
Resource (Paper (.PDF)) - Feb 17, 2025 by Harry Foster
This report examines the trends in functional verification for the field programmable gate array (FPGA) market segments identified in the 2024 Wilson Research Group study.
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Verification Effectiveness Trends
Session - Feb 17, 2025 by Harry Foster
Explore how verification effectiveness is measured across the industry, including trends in first-silicon success rates, coverage closure, and the growing complexity of verification challenges.
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Verification Effort Trends
Session - Feb 17, 2025 by Harry Foster
Dive into the resource demands of verification, including team sizes, effort distribution between design and verification, and how companies are adapting to increasing verification workloads.
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Design Trends
Session - Feb 17, 2025 by Harry Foster
Examine shifts in ASIC and FPGA design complexity, IP reuse, and project scalability, along with insights into how these trends impact verification strategies.
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Language and Methodology Trends
Session - Feb 17, 2025 by Harry Foster
Review the latest trends in design and verification languages, including the adoption of SystemVerilog, UVM, and other methodologies that influence verification efficiency.
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Verification Technology Trends
Session - Feb 17, 2025 by Harry Foster
Take a closer look at the adoption of advanced verification technologies such as formal verification, simulation, emulation, FPGA prototyping, and their impact on verification workflows.
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Final Insights and Conclusions
Session - Feb 17, 2025 by Harry Foster
Summarizing key takeaways from the study, this video highlights the most significant trends, challenges, and opportunities shaping the future of ASIC and FPGA verification.
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Got Coverage?
Resource (Verification Horizons Blog) - Feb 14, 2025 by Rich Edelman
Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of coverage. Got Coverage? But, nevermind – what about YOUR coverage!? You didn’t get enough coverage collected. But just maybe you have a bunch of 0’s and 1’s. You’re late with your coverage, but your old school 0’s and 1’s are going to save the day.
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DVCon 2025: A Must for Hardware Design and Verification Engineers
Resource (Verification Horizons Blog) - Feb 12, 2025 by Dave Rich
I’ve attended every DVCon US conference since its inception, over 30 years ago. I’ve also given keynotes at DVCon India. Now I’m the DVCon US vice program chair and am looking forward to being the program chair in 2026. I can honestly say this conference is an unparalleled opportunity for design and verification engineers. DVCon U.S. 2025 continues to uphold the DVCon reputation as the premiere event for our community, offering a unique venue to learn, network, and exchange ideas face-to-face.
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Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator
Resource (Slides (.PDF)) - Feb 12, 2025 by Mark Carey
In this webinar, we explore the powerful smart regression features of collaborative browser-based data-driven verification. You will then learn how to harness the full potential of Questa Verification IQ to boost efficiency and productivity in your verification efforts, take advantage of automating the detection of design differences and optimize regression time by maximizing compute resources.
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Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator
Webinar - Feb 12, 2025 by Mark Carey
In this webinar, we explore the powerful smart regression features of collaborative browser-based data-driven verification. You will then learn how to harness the full potential of Questa Verification IQ to boost efficiency and productivity in your verification efforts, take advantage of automating the detection of design differences and optimize regression time by maximizing compute resources.
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Siemens at DVCon 2025: Don’t Miss the Luncheon and More!
Resource (Verification Horizons Blog) - Feb 11, 2025 by Harry Foster
The latest trends in verification are in—and they’re more than just surprising. They’re alarming . Join Siemens EDA at DVCon 2025 for an exclusive luncheon presentation on February 25th, from 12:30 PM to 1:30 PM , where industry leaders will break down the biggest challenges shaping today’s verification landscape and how Siemens is addressing these challenges.
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Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard
Resource (Verification Horizons Blog) - Feb 10, 2025 by Dennis Brophy
Accellera Systems Initiative approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard. This milestone marks a significant advancement in the verification of analog/mixed-signal (AMS) and digital/mixed-signal (DMS) integrated circuits and systems. UVM is widely used around the world but has struggled to work well with designs that have analog/mixed-signal blocks. This is now changed. And it has also given rise to a new logo from Accellera.
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Smart Verification with AI/ML: Smart Regression & Smart Debug
Resource (Slides (.PDF)) - Feb 06, 2025 by Austin Mam
Leverage the power of AI and ML! Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allow engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.
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Leveraging Trust and Security Analysis to Meet Design Assurance Requirements
Resource (Slides (.PDF)) - Feb 06, 2025 by David Landoll
Learn about the effectiveness of enhancing security verification and improving the robustness of your hardware security verification through detailed explanations and runtime insights. Explore methods to protect against data corruption using formal security verification techniques.
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Integrating the Value of Questa Design Solutions in a Continuous Integration Development Flow
Resource (Slides (.PDF)) - Feb 06, 2025 by Walter Gude
Learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
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Enhancing Productivity in Simulation-Based Functional Verification
Resource (Slides (.PDF)) - Feb 06, 2025 by Moses Satyasekaran
Improving productivity has become crucial for efficiently utilizing expensive human and grid resources in the functional verification process. Achieving the "done" state requires more than simulator performance - it demands a strategic focus on optimizing workflows, prioritizing tasks, and leveraging metrics to guide efforts. A productivity-driven approach ensures resources are deployed effectively, accelerating verification closure.
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VA Live - El Segundo: Introduction and Welcome
Resource (Slides (.PDF)) - Feb 06, 2025 by Todd Holbrook
Welcome to Verification Academy Live.