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Optimizing Emulator Utilization
Article - Jun 16, 2014 by Russell Klein
Emulators, like Siemens EDA Veloce, are able to run designs in RTL orders of magnitude faster than logic simulators. As a result, emulation is used to execute verification runs which would be otherwise impractical in logic simulation.
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MIPI LLI Verification using Questa Verification IP
Article - Jun 16, 2014 by Vaibhav Gupta - Siemens EDA
In this article, we will discuss how sequence items are useful to generate stimulus on multiple layers of LLI QVIP, how the combination of LLI QVIP based on coverage-driven methodology and protocol capturing XML plans can boost verification completeness, how the combination of protocol assertions and error injection method is useful to generate the error scenario, check the behavior of the LLI design, and how the scoreboard is useful to check the data integrity between LLI design and LLI QVIP.
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Stories of an AMS Verification Dude: Model Shmodel
Article - Jun 16, 2014 by Martin Vlach
Well here I am again. Last time I talked about putting stuff together, and when I mean stuff, it turned out that the digital folks handed me an RTL and the analog dudes gave me a SPICE netlist. I finally got it all working together, and let ‘er rip, thinking that this was easy and I’ll be done in no time. But that “no time” turned into hours, and then days, and then nights, too.
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Merging SystemVerilog Covergroups by Example
Article - Jun 16, 2014 by Eldon Nelson - Micron
This article describes the effect of implementing covergroup choices on how the resulting covergroup behaves when merged. The source code of the examples, along with their structural diagrams, as well as screen shots of the resulting covergroups, taken from Mentor Questa, will help illustrate those choices in a simple way.
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Increasing Verification Productivity Through Functional Coverage Management Automation
Article - Jun 16, 2014 by Samrat Patel, Vipul Patel - eInfochips
This article describes a simple methodology which addresses all the above issues. It uses the concept of inheritance and can be implemented as a tool in conjunction with Questa. This customization methodology can be used across all protocols.
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Use of Iterative Weight-Age Constraint to Implement Dynamic Verification Components
Article - Jun 16, 2014 by Mahak Singh, Siddhartha Mukherjee - Truechip
In this article we will explain how weight-age constraints can be used for randomized verification with maximum coverage near the corners and some coverage in the middle, thus saving verification time and getting good coverage faster.
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UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment
Article - Jun 16, 2014 by Mihajlo Katona - Veriest
This article discusses how a UVM verification environment was set up easily for a mixed signal device under test (DUT) using a scripting tool developed in-house and based on a testbench configuration file. The article focuses mostly on presenting two mixed signal DUT examples and the corresponding UVM-based testbench with a digital-ontop structure.
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UVM 1.2 Class Reference
Resource (Reference Documentation) - Jun 13, 2014 by
v1.2 The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
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Stories of an AMS Verification Dude: Putting Stuff Together
Article - Jun 12, 2014 by Verification Horizons
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Taming Power Aware Bugs with Questa®
Article - Jun 12, 2014 by Verification Horizons
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UVM 1.2 is Coming, so be Prepared
Webinar - May 15, 2014 by Tom Fitzpatrick
In this session, you will learn everything you need to know about the future of UVM including new features, performance, backward-compatibility concerns and more.
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Verification Cookbook Glossary
Chapter - Mar 31, 2014 by Verification Methodology Team
This page is an index to the glossary of various terms defined and used in the Cookbook.
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Sequence Library
Chapter - Mar 31, 2014 by Verification Methodology Team
Updating your VIP/testbench sequence library is one task that you may have to perform while migrating from OVM to UVM.
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Convert Phase Methods
Chapter - Mar 31, 2014 by Verification Methodology Team
Part of the OVM to UVM conversion process is to change the method names for OVM phase methods (build, connect, run, etc) to the new UVM signature for phase methods.
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Migrating from OVM to UVM
Chapter - Mar 31, 2014 by Verification Methodology Team
A Roadmap for upgrading to UVM - this guide covers the minimum steps to upgrade your VIP and testbench from OVM to UVM compatibility, then goes into more detail on some further steps for UVM conformance.
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Questa Compiling UVM
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM class library is an open source SystemVerilog package that relies on DPI c code in order to implement some of the library features such as regular expression matching and register backdoor accesses.
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Deprecated Code
Chapter - Mar 31, 2014 by Verification Methodology Team
Accellera UVM1.0 used OVM2.1.1 as it's basis, with the intention of preserving backwards compatibility where possible.
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Phase Aware
Chapter - Mar 31, 2014 by Verification Methodology Team
OVM code can be ported to run on the UVM.
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Arbitrating Between Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
The uvm_sequencer has a built-in mechanism to arbitrate between sequences which could be running concurrently on a sequencer.
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UVM Configuration Database
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM_config_db class is the recommended way to access the resource database.
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Sequence API
Chapter - Mar 31, 2014 by Verification Methodology Team
A uvm_sequence is derived from an uvm_sequence_item and it is parameterized with the type of sequence_item that it will send to a driver via a sequencer.
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Reporting Verbosity
Chapter - Mar 31, 2014 by Verification Methodology Team
UVM provides a built-in mechanism to control how many messages are printed in a UVM based testbench. This mechanism is based on comparing integer values specified when creating a debug message using either the uvm_report_info() function or the `uvm_info() macro.
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Built in Debug
Chapter - Mar 31, 2014 by Verification Methodology Team
Learn about various debug techniques and support for SystemVerilog and UVM with features supplied with the UVM to assist in common problem debug.
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Matlab Integration
Chapter - Mar 31, 2014 by Verification Methodology Team
MATLAB is a modeling tool often used to develop functional models of complex mathematical functions which will then be translated into RTL library blocks.
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UVM Phasing
Chapter - Mar 31, 2014 by Verification Methodology Team
Phasing is a stepwise construction approach of a verification environment at runtime and the execution of required stimulus and completion of the test. UVM has an API enabling components to participate in this step by step process. The construction of structured test environments with TLM connections is done in a predetermined manner to enable smart hierarchy and connectivity management. Most verification environments use the simplest possible subset of the available phases: build, connect, run.