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UVM Sequence Items

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM stimulus generation process is based on sequences controlling the behavior of drivers by generating sequence_items and sending them to the driver via a sequencer.
Register Package

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM register model provides a way of tracking the register content of a DUT and a convenience layer for accessing register and memory locations within the DUT.
UVM Guidelines

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM library is both a collection of classes and a methodology for how to use those base classes.
Register Layer Adapter

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM register model access methods generate bus read and write cycles using generic register transactions.
UVM Performance Guidelines

Chapter - Mar 31, 2014 by Verification Methodology Team

Although the UVM improves verification productivity, there are certain aspects of the methodology that should be used with caution, or perhaps not at all, when it comes to performance and scalability considerations.
Register-Level Scoreboards

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM register model shadows the current configuration of a programmable DUT and this makes it a valuable resource for scoreboards that need to be aware of the current DUT state.
Sequence Driver Connection

Chapter - Mar 31, 2014 by Verification Methodology Team

The transfer of request and response sequence items between sequences and their target driver is facilitated by a bidirectional TLM communication mechanism implemented in the sequencer.
C Based Stimulus

Chapter - Mar 31, 2014 by Verification Methodology Team

Using c to generate stimulus via the UVM register package.
Predictors

Chapter - Mar 31, 2014 by Verification Methodology Team

A Predictor is a verification component that represents a "golden" reference model of all or part of the DUT functionality.
SystemVerilog Guidelines

Chapter - Mar 31, 2014 by Verification Methodology Team

The SystemVerilog coding guidelines and rules in this article are based on Siemens EDA's experience and are designed to steer users away from coding practices that result in SystemVerilog that is either hard to understand or debug.
Generating Stimulus with UVM Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

The uvm_sequence_base class extends the uvm_sequence_item class by adding a body task method.
Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

Sequences are used to encapsulate stimulus, Sequencer/Driver hookup, pipelined protocols, test generation, performance analysis and much more.
Unidirectional Protocols

Chapter - Mar 31, 2014 by Verification Methodology Team

For a driver, composed of a BFM-proxy pair in the dual domain testbench, the driver proxy controls the flow of sequence_items by using get_next_item() to obtain the next sequence_item to be processed, and making the item_done() call only once it has finished processing the item.
Sequence-Driver Use Models

Chapter - Mar 31, 2014 by Verification Methodology Team

Sequence-Driver Use Models can be applied to both pipelined and non-pipelined models in hardware verification.
Driver Sequence API

Chapter - Mar 31, 2014 by Verification Methodology Team

The uvm_driver is an extension of the uvm_component class that adds an uvm_seq_item_pull_port which is used to communicate with a sequence via a sequencer.
Bidirectional Protocols

Chapter - Mar 31, 2014 by Verification Methodology Team

For a driver, composed of a BFM-proxy pair in the dual domain testbench, one of the most common sequence-driver use cases is where the sequencer sends request sequence_items to the driver proxy, which then executes the request phase of the pin-level protocol through the driver BFM.
Analysis

Chapter - Mar 31, 2014 by Verification Methodology Team

Components in a UVM testbench that observe and analyze behavior of the DUT.
Analysis Port

Chapter - Mar 31, 2014 by Verification Methodology Team

One of the unique aspects of the analysis section of a testbench is that usually there are many independent calculations and evaluations all operating on the same piece of data.
Analysis Connections

Chapter - Mar 31, 2014 by Verification Methodology Team

An analysis component such as a Monitor sends transactions to another analysis component through a TLM connection which is a chain of objects where each calls the write(t) function in the next.
Configuring Registers

Chapter - Mar 31, 2014 by Verification Methodology Team

During verification a programmable hardware device needs to be configured to operate in different modes. The register model can be used to automate or to semi-automate this process.
Built-in Register Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM package contains a library of automatic test sequences which are based on the register model. These sequences can be used to do basic tests on registers and memory regions within a DUT.
Metric Analyzers

Chapter - Mar 31, 2014 by Verification Methodology Team

Metric Analyzers watch and record non-functional behavior such as latency, power utilization, and other performance-related measurements.
Objections

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM_objection class provides a means for sharing a counter between participating components and sequences.
Separate Top-Level Modules

Chapter - Mar 31, 2014 by Verification Methodology Team

Co-emulation is done by running two distinct synchronized model evaluations - one on a hardware emulator, and one on a software simulator.
Split Transactors

Chapter - Mar 31, 2014 by Verification Methodology Team

Driver and monitor transactors contain a mixture of transaction-level code to communicate with the testbench, and clock-driven HDL signal accessing code to communicate with the DUT through a virtual interface.

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Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

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Chapter - Mar 31, 2014 by Verification Methodology Team

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Chapter - Mar 31, 2014 by Verification Methodology Team

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Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team