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UVM Tips and Tricks

Article - Mar 01, 2017 Sandeep Nasa, Shankar Arora - Logic Fruit Technologies Pvt. Ltd.

UVM is the most widely used Verification methodology for functional verification of digital hardware (described using Verilog, SystemVerilog or VHDL at appropriate abstraction level). It is based on OVM and is developed by Accellera. It consists of base libraries written in SystemVerilog which enables the end user to create testbench components faster using these base libraries.
Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation

Article - Mar 01, 2017 Progyna Khondkar

The Questa Power Aware (PA) dynamic simulator (PA-SIM) provides a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from target design implementation objectives.
Complementing Functional Verification Through the Use of Available Timing Information

Article - Mar 01, 2017 Rick Eram - Excellicon

Since the advent of formal techniques, the application of formal analysis has helped designers achieve more in-depth analysis and coverage of functional verification activities in general. However what has spurred the growth and popularity of such techniques has been specific and targeted applications of formal analysis.
DPI Redux. Functionality. Speed. Optimization.

Resource (Paper (.PDF)) - Feb 28, 2017 Rich Edelman

This paper will explore SystemVerilog DPI-C for the new user as well as the experienced user. After reading this paper, the reader should feel comfortable using SystemVerilog DPI-C to help solve their verification needs.
DPI Redux. Functionality. Speed. Optimization.

Paper - Feb 28, 2017 Rich Edelman

SystemVerilog DPI-C is commonly used for many different things - all interfacing SystemVerilog with C. Although well used in places, it is not uniformly used, nor is it used always in optimal ways. This paper will revisit the DPI-C use model, suggest common usage and recommend preferred optimizations.
How Formal Reduces Fault Analysis for ISO 26262

Paper - Feb 15, 2017 Doug Smith

In this white paper, we will discuss how to use formal verification for static and transient fault analysis to generate the ISO 26262 safety metrics. First, we will look at some of the low-hanging fruit that formal analysis provides, and then we will discuss how to tackle the much harder task of fault injection.
How Formal Reduces Fault Analysis for ISO 26262

Resource (Paper (.PDF)) - Feb 15, 2017 Doug Smith

This paper discusses how to use formal verification for static and transient fault analysis to generate ISO 26262 safety metrics, first describing fault pruning and then the more sophisticated fault injection using SLEC.
Questa VRM and Jenkins

Track - Jan 10, 2017 Darron May

This track will define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project.
Jenkins Installation and Setup

Session - Jan 10, 2017 Darron May

In this session, you will be introduced to the Jenkins continuous integration system, along with step-by-step installation and setup instructions.
Jenkins Project Configuration

Session - Jan 10, 2017 Darron May

In this session, we will walk through the project configuration and how to setup a job with the Questa VRM plug-in.
Jenkins VRM Integration

Demo - Jan 10, 2017 Darron May

In this session, we will demo the Questa VRM Jenkins integration, and you will see firsthand how to execute tests and generate reports.
The Fundamental Power States for UPF Modeling and Power Aware Verification

Article - Jan 04, 2017 Verification Methodology Team
Introspection Into SystemVerilog Without Turning It Inside Out

Article - Jan 03, 2017 Dave Rich
UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process

Article - Jan 03, 2017 Verification Methodology Team
Interpreting UPF For A Mixed-Signal Design Under Test

Article - Jan 03, 2017 Verification Methodology Team
Is Your Power Aware Design Really X-Aware?

Article - Jan 03, 2017 Verification Methodology Team
Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification

Article - Jan 03, 2017 Verification Methodology Team
So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results

Article - Jan 03, 2017 Andreas Meyer
Conclusion: Deeper Dive into Non-Trivial Bug Escapes and Safety Critical Designs

Resource (Verification Horizons Blog) - Jan 03, 2017 Harry Foster

In my previous blog, I presented verification results in terms of schedules, number of required spins, and classification of functional bugs. In this blog, I conclude the series by having a little fun with some of the findings from our recent study. You might recall from our 2014 study we did a deeper dive into the findings made a non-intuitive observation related to design size and first silicon success. That is, the smaller the design the less likelihood of achieving first silicon success.
Jenkins Tutorial - Setup, Install, Configuration

Resource (Reference Documentation) - Dec 23, 2016 Darron May

Questa VRM 10.5 has native support to allow use with the Questa VRM Jenkins plug-in. This plug-in will be made available on the Jenkins plug-in website once it is released but currently has to be installed from a file. This document gathers a few notes on how to install Jenkins, install the plug-in and set-up a demo design with Jenkins running VRM.
JUnit Plugin (required)

Resource (Reference Documentation) - Dec 23, 2016
Questa VRM

Resource (Reference Documentation) - Dec 23, 2016 Darron May

This plugin adds the ability for Jenkins to publish results from Questa Verification Run Manager (VRM).
Jenkins Release

Resource (Reference Documentation) - Dec 23, 2016

The leading open source automation server, Jenkins provides hundreds of plugins to support building, deploying and automating any project.
Dashboard View (optional)

Resource (Reference Documentation) - Dec 23, 2016
Five Common Pitfalls to Avoid While Verifying PCIe® Based NVMe Controllers

Paper - Dec 19, 2016 Saurabh Sharma - Siemens EDA

NVMe is gaining rapidly in mindshare among consumers and vendors. Some industry analysts are forecasting that PCIe® based NVMe will become the dominant storage interface over the next few years. With its high-performance and low-latency characteristics, and its availability for virtually all platforms, NVMe is a game changer. For the first time, storage devices and storage subsystems have a fundamentally different way to operate with host computers, unlike any previous storage protocol.