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Sequence Library

Chapter - Mar 31, 2014 by Verification Methodology Team

Updating your VIP/testbench sequence library is one task that you may have to perform while migrating from OVM to UVM.
Convert Phase Methods

Chapter - Mar 31, 2014 by Verification Methodology Team

Part of the OVM to UVM conversion process is to change the method names for OVM phase methods (build, connect, run, etc) to the new UVM signature for phase methods.
Migrating from OVM to UVM

Chapter - Mar 31, 2014 by Verification Methodology Team

A Roadmap for upgrading to UVM - this guide covers the minimum steps to upgrade your VIP and testbench from OVM to UVM compatibility, then goes into more detail on some further steps for UVM conformance.
Questa Compiling UVM

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM class library is an open source SystemVerilog package that relies on DPI c code in order to implement some of the library features such as regular expression matching and register backdoor accesses.
Deprecated Code

Chapter - Mar 31, 2014 by Verification Methodology Team

Accellera UVM1.0 used OVM2.1.1 as it's basis, with the intention of preserving backwards compatibility where possible.
Phase Aware

Chapter - Mar 31, 2014 by Verification Methodology Team

OVM code can be ported to run on the UVM.
Arbitrating Between Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

The uvm_sequencer has a built-in mechanism to arbitrate between sequences which could be running concurrently on a sequencer.
UVM Configuration Database

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM_config_db class is the recommended way to access the resource database.
Sequence API

Chapter - Mar 31, 2014 by Verification Methodology Team

A uvm_sequence is derived from an uvm_sequence_item and it is parameterized with the type of sequence_item that it will send to a driver via a sequencer.
Reporting Verbosity

Chapter - Mar 31, 2014 by Verification Methodology Team

UVM provides a built-in mechanism to control how many messages are printed in a UVM based testbench. This mechanism is based on comparing integer values specified when creating a debug message using either the uvm_report_info() function or the `uvm_info() macro.
Built in Debug

Chapter - Mar 31, 2014 by Verification Methodology Team

Learn about various debug techniques and support for SystemVerilog and UVM with features supplied with the UVM to assist in common problem debug.
Matlab Integration

Chapter - Mar 31, 2014 by Verification Methodology Team

MATLAB is a modeling tool often used to develop functional models of complex mathematical functions which will then be translated into RTL library blocks.
UVM Phasing

Chapter - Mar 31, 2014 by Verification Methodology Team

Phasing is a stepwise construction approach of a verification environment at runtime and the execution of required stimulus and completion of the test. UVM has an API enabling components to participate in this step by step process. The construction of structured test environments with TLM connections is done in a predetermined manner to enable smart hierarchy and connectivity management. Most verification environments use the simplest possible subset of the available phases: build, connect, run.
Accessing Configuration Resources from a Sequence

Chapter - Mar 31, 2014 by Verification Methodology Team

Sequences often need access to testbench resources such as register models or configuration objects.
Testbench Configuration

Chapter - Mar 31, 2014 by Verification Methodology Team

One of the key tenets of designing reusable testbenches is to make testbenches as configurable as possible. Doing this means that the testbench and its constituent parts can easily be reused and quickly modified (i.e. reconfigured).
UVM Packages

Chapter - Mar 31, 2014 by Verification Methodology Team

A package is a SystemVerilog language construct that enables related declarations and definitions to be grouped together in a package namespace.
Dual Top Architecture

Chapter - Mar 31, 2014 by Verification Methodology Team

The dual top testbench architecture advocated throughout this cookbook enables platform portability - it is fundamental for testbench acceleration using emulation or some other hardware-assisted platform.
Parameterized Tests

Chapter - Mar 31, 2014 by Verification Methodology Team

SystemVerilog provides a number of ways to pass changeable values through different code structures. Some changeable values must be fixed at elaboration time and others can be changed at run-time after starting a simulation.
Testbench Build

Chapter - Mar 31, 2014 by Verification Methodology Team

The first phase of a UVM testbench is the build phase. During this phase, the uvm_component classes that make up the testbench hierarchy are constructed into objects.
Configuring Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

A frequently encountered scenario in sequence configuration involves setting up the agent's configuration object, encompassing its constituent components such as the sequencer, driver, monitor, and more.
UVM Agent

Chapter - Mar 31, 2014 by Verification Methodology Team

A UVM agent is a verification component "kit" for a given logical interface such as APB or USB.
Emulation

Chapter - Mar 31, 2014 by Verification Methodology Team

Learn all about methodology related to Veloce/TBX Emulation on UVM.
Using a Parameter Package

Chapter - Mar 31, 2014 by Verification Methodology Team

When a DUT or interface is parameterized, the parameter values are almost always used in the testbench as well.
Macro Cost-Benefit Analysis

Chapter - Mar 31, 2014 by Verification Methodology Team

Macros can be useful to reduce repetitive typing of small pattern-like code segments, to hide implementation differences or limitations among the simulators from different vendors, or to make critical code segments less error-prone for reuse.
SystemVerilog Performance Guidelines

Chapter - Mar 31, 2014 by Verification Methodology Team

These guidelines are aimed at enabling you to identify coding idioms that are likely to affect testbench performance.

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