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24x7 Productivity: Veloce® Enterprise Server App Does the Job

Article - Nov 07, 2016 by Vijay Chobisa

The way companies use hardware emulation has changed. Historically, emulators were used in a lab, at one location, executing one job at a time. Because of this, an emulator often sat idle. In this scenario, project scheduling for the emulator was done manually by allocating fixed time slots to project teams. An inherently inflexible and inefficient way to manage a valuable resource, especially for global teams.
Power Aware Libraries: Standardization and Requirements for Questa Power Aware

Article - Nov 07, 2016 by Progyna Khondkar

Multi-voltage (MV) based power-ware (PA) design verification and implementation methodologies require special power management attributes in libraries for standard, MV and Macro cells for two distinctive reasons.
Improving Performance and Verification of a System Through an Intelligent Testbench

Article - Nov 07, 2016 by Umesh Patel, Dhaval Shah - Arastu Systems Pvt. Ltd.

The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step closer towards achieving more confidence in design with minimal engineering effort. Applications today demand diverse functionality, which results in complex to very complex designs.
Part 10: IC/ASIC Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Oct 31, 2016 by Harry Foster

In my previous blog, I focused on I various verification technology adoption trends. In this blog I plan to discuss various IC/ASIC language and library adoption trends. Fig. 10-1 shows the adoption trends for languages used to create RTL designs. Essentially, the adoption rates for all languages used to create RTL designs is projected to be either declining or flat over the next year.
Functional Verification Study - 2016

Session - Oct 14, 2016 by Harry Foster

In this session, Harry Foster highlights the key findings from the 2016 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
Part 9: IC/ASIC Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Oct 10, 2016 by Harry Foster

In my previous blog, I focused on the growing IC/ASIC design project resource trends due to rising design complexity. In this blog I examine various verification technology adoption trends. Fig. 9-1 shows the IC/ASIC adoption trends for various simulation-based techniques from 2007 through 2016, which include code coverage, assertions, functional coverage, and constrained-random simulation.
Part 8: IC/ASIC Resource Trends

Resource (Verification Horizons Blog) - Oct 04, 2016 by Harry Foster

In my previous blog, I focused on FPGA design and verification trends. I now will shift the focus of this series of blogs from FPGA trends to IC/ASIC trends. In this blog, I plan to discuss the growing IC/ASIC design project resource trends due to rising design complexity. Fig. 8-1 shows the percentage of total project time spent in verification. As you would expect, the results are all over the spectrum; whereas, some projects spend less time in verification, other projects spend more.
Part 7: IC/ASIC Design Trends

Resource (Verification Horizons Blog) - Sep 25, 2016 by Harry Foster

In my previous blog, focused on FPGA design and verification trends. I now will shift the focus of this series of blogs from FPGA trends to IC/ASIC trends. In this blog, I present trends related to various aspects of design to illustrate growing design complexity. Fig. 7-1 shows the trends from the 2014 and 2016 studies in terms of active IC/ASIC design project by design sizes (gates of logic and datapath, excluding memories).
Part 6: FPGA Verification Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Sep 21, 2016 by Harry Foster

In my previous blog, I focused on FPGA verification techniques and technologies adoption trends, as identified by the 2016 Wilson Research Group study. In this blog, I’ll present FPGA design and verification language trends. You might note that the percentage for some of the language that I present sums to more than one hundred percent. The reason for this is that many FPGA projects today use multiple languages.
Part 5: FPGA Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Sep 11, 2016 by Harry Foster

In this blog, I present verification techniques and technologies adoption trends, as identified by the 2016 Wilson Research Group study. An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was five years ago in terms of verification maturity—and it is catching up quickly. A question you might ask is, “What is driving this trend?”
Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy

Webinar - Sep 09, 2016 by Gordon Allan

In this session we will deliver five steps your team can take to improve first pass success, and how Questa enables your advanced verification goals every step of the way.
Part 4: FPGA Verification Effectiveness Trends

Resource (Verification Horizons Blog) - Sep 07, 2016 by Harry Foster

In my previous blog, I focused on the amount of effort spent in FPGA verification. We have seen in previous blogs that an increasing amount of effort is being applied to FPGA functional verification. In this blog I focus on the effectiveness of verification in terms of FPGA project schedule and bug escapes.
Part 3: FPGA Verification Effort Trends (Continued)

Resource (Verification Horizons Blog) - Aug 29, 2016 by Harry Foster

In my previous blog I focused on the controversial topic of effort spent in FPGA verification. This blog continues that discussion. I stated in my previous blog that I don’t believe there is a simple answer to the question, “how much effort was spent on verification in your last FPGA project?” I believe that it is necessary to look at multiple data points to truly get a sense of the real effort involved in verification today. So, let’s look at a few additional findings from the study.
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

Paper - Aug 26, 2016 by Kurt Takara

In this paper, we begin by discussing the low power challenges for CDC design and verification including dynamic frequency and voltage scaling (DVFS). The following section describes the low power CDC verification methods and how these methods address the low power issues. Finally, we review some application examples for low power DVFS CDC verification.
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

Resource (Paper (.PDF)) - Aug 26, 2016 by Kurt Takara

With the advances in low power design, new low power artifacts have been introduced that cannot be detected with traditional verification techniques and may cause clock domain crossing (CDC) issues in silicon. This paper explains the new low power CDC issues and the CDC and voltage domain crossing (VDC) verification techniques developed to verify low power designs.
Extending a Traditional VIP to Solve PHY Verification Challenges

Resource (Paper (.PDF)) - Aug 26, 2016 by
Total Recall - What to Look for in a Memory Model Library

Resource (Paper (.PDF)) - Aug 24, 2016 by
SystemVerilog Code Examples

Resource (Tarball) - Aug 24, 2016 by Ray Salemi

This file contains the PDF and the example files from the SystemVerilog Primer for VHDL engineers.
Article: How to instrument your design with simple SystemVerilog assertions

Resource - Aug 24, 2016 by
SystemVerilog & UVM Coding & Performance Guidelines

Resource (Reference Documentation) - Aug 24, 2016 by
Technical Paper: A Scalable Approach for TLM Across SystemC and SystemVerilog

Resource - Aug 24, 2016 by
Technical Paper: Towards an Object-Oriented Design Methodology Using SystemVerilog

Resource - Aug 24, 2016 by
SystemVerilog Performance Guide

Resource (Reference Documentation) - Aug 24, 2016 by VM Team

These guidelines are aimed at enabling you to identify coding idioms that are likely to affect testbench performance. Please note that a number of these guidelines run counter to other recommended coding practices and a balanced view of the tradeoff between performance and methodology needs to be made.
SystemVerilog Assertions Design Tricks & SVA Bind Files (slide set 4)

Resource - Aug 24, 2016 by
SystemVerilog Coding Guide

Resource (Reference Documentation) - Aug 24, 2016 by VM Team

The SystemVerilog coding guidelines and rules in this article are based on Siemens EDA’s experience and are designed to steer users away from coding practices that result in SystemVerilog that is either hard to understand or debug.