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Unidirectional Protocols

Chapter - Mar 31, 2014 by Verification Methodology Team

For a driver, composed of a BFM-proxy pair in the dual domain testbench, the driver proxy controls the flow of sequence_items by using get_next_item() to obtain the next sequence_item to be processed, and making the item_done() call only once it has finished processing the item.
Sequence-Driver Use Models

Chapter - Mar 31, 2014 by Verification Methodology Team

Sequence-Driver Use Models can be applied to both pipelined and non-pipelined models in hardware verification.
Driver Sequence API

Chapter - Mar 31, 2014 by Verification Methodology Team

The uvm_driver is an extension of the uvm_component class that adds an uvm_seq_item_pull_port which is used to communicate with a sequence via a sequencer.
Bidirectional Protocols

Chapter - Mar 31, 2014 by Verification Methodology Team

For a driver, composed of a BFM-proxy pair in the dual domain testbench, one of the most common sequence-driver use cases is where the sequencer sends request sequence_items to the driver proxy, which then executes the request phase of the pin-level protocol through the driver BFM.
Analysis

Chapter - Mar 31, 2014 by Verification Methodology Team

Components in a UVM testbench that observe and analyze behavior of the DUT.
Analysis Port

Chapter - Mar 31, 2014 by Verification Methodology Team

One of the unique aspects of the analysis section of a testbench is that usually there are many independent calculations and evaluations all operating on the same piece of data.
Analysis Connections

Chapter - Mar 31, 2014 by Verification Methodology Team

An analysis component such as a Monitor sends transactions to another analysis component through a TLM connection which is a chain of objects where each calls the write(t) function in the next.
Configuring Registers

Chapter - Mar 31, 2014 by Verification Methodology Team

During verification a programmable hardware device needs to be configured to operate in different modes. The register model can be used to automate or to semi-automate this process.
Built-in Register Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM package contains a library of automatic test sequences which are based on the register model. These sequences can be used to do basic tests on registers and memory regions within a DUT.
Metric Analyzers

Chapter - Mar 31, 2014 by Verification Methodology Team

Metric Analyzers watch and record non-functional behavior such as latency, power utilization, and other performance-related measurements.
Objections

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM_objection class provides a means for sharing a counter between participating components and sequences.
Separate Top-Level Modules

Chapter - Mar 31, 2014 by Verification Methodology Team

Co-emulation is done by running two distinct synchronized model evaluations - one on a hardware emulator, and one on a software simulator.
Split Transactors

Chapter - Mar 31, 2014 by Verification Methodology Team

Driver and monitor transactors contain a mixture of transaction-level code to communicate with the testbench, and clock-driven HDL signal accessing code to communicate with the DUT through a virtual interface.
Back Pointers

Chapter - Mar 31, 2014 by Verification Methodology Team

In the original single top bidirectional driver example, all driver activity is initiated from the testbench domain.
Defining an API

Chapter - Mar 31, 2014 by Verification Methodology Team

As the timed portion of the traditional UVM transactor must be moved over to the HDL domain.
Emulation-Ready Testbench Examples

Chapter - Mar 31, 2014 by Verification Methodology Team

This article steps through the process of converting a comprehensive traditional single top UVM example testbench to an equivalent one with a dual domain partitioned structure that is ready for co-emulation with Veloce.
Sequence Priority

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM sequence use model allows multiple sequences to access a driver concurrently.
Overriding Sequences and Sequence Items

Chapter - Mar 31, 2014 by Verification Methodology Team

Sometimes, during stimulus generation, it is useful to change the behavior of sequences or sequence items.
Layering Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

Many protocols have a hierarchical definition - for example, PCI express, USB 3.0, and MIPI LLI all have a Transaction Layer, a Transport Layer, and a Physical Layer.
Locking or Grabbing a Sequencer

Chapter - Mar 31, 2014 by Verification Methodology Team

There are a number of modeling scenarios where one sequence needs to have exclusive access to a driver via a sequencer.
Hierarchical Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

When dealing with sequences, it helps to think in layers when considering the different functions that a testbench will be asked to perform.
Register-Level Stimulus

Chapter - Mar 31, 2014 by Verification Methodology Team

Stimulus that accesses memory mapped registers should be made as abstract as possible.
Register Model & Structure

Chapter - Mar 31, 2014 by Verification Methodology Team

In order to be able to use the UVM register model effectively, it is important to have a mental model of how it is structured in order to be able to find your way around it.
Register Sequence Examples

Chapter - Mar 31, 2014 by Verification Methodology Team

To illustrate how the different register model access methods can be used from sequences to generate stimulus, this page contains a number of example sequences developed for stimulating the SPI master controller DUT.
Generating Register Models

Chapter - Mar 31, 2014 by Verification Methodology Team

A register model can be written by hand, following the pattern given for the SPI master example.

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Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team