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Unit Testing Your Way to a Reliable Testbench

Article - Jun 06, 2015 by Neil Johnson

Writing tests, particularly unit tests, can be a tedious chore. More tedious - not to mention frustrating - is debugging testbench code as project schedules tighten and release pressure builds. With quality being a non-negotiable aspect of hardware development, verification is a pay-me-now or pay-me-later activity that cannot be avoided.
Hardware Emulation: Three Decades of Evolution – Part II

Article - Jun 06, 2015 by Dr. Lauro Rizzatti - Rizzatti LLC

In the second decade, the hardware emulation landscape changed considerably with a few mergers and acquisitions and new players entering the market. The hardware emulators improved notably via new architectures based on custom ASICs.
Accelerating RTL Simulation Techniques

Article - Jun 06, 2015 by Lior Grinzaig - Marvell

Long simulation run times are a bottleneck in the verification process. Coding style has a significant effect on simulation run times. Therefore, it is imperative that the code writer examine his/her code, not only by asking the question “does the code produce the desired output?” but also “is the code economical, and if not, what can be done to improve it?”
Emulation Based Approach to ISO 26262 Compliant Processors Design

Article - Jun 06, 2015 by David Kaushinsky - Siemens EDA

This article reviews the use of processors in the automotive industry, the origin of faults in processors, architectures of fault tolerant processors and techniques for processor verification with fault injection. We then propose an emulation-based framework for performing fault-injection experiments on embedded processor architectures.
Resolving the Limitations of a Traditional VIP for PHY Verification

Article - Jun 06, 2015 by Amit Tanwar, Manoj Manu - Siemens EDA

This article describes the limitations of a traditional VIP for PHY verification, which can typically be resolved using an exclusive PHY verification kit. The common PHY found in PCI Express, USB 3.0 and 3.1, and SATA devices help accelerate development of these devices by implementing the physical layer functionality as a discreet IC or macro cell, which can be easily included in ASIC designs.
Automatic Formal Solutions

Track - Jun 05, 2015 by Mark Eslinger

After a brief introductory session outlining the general architecture of formal apps, in each subsequent session of this track will deep dive on a specific verification challenge and the corresponding formal application.
Introduction to Automated Formal Apps

Session - Jun 05, 2015 by Joe Hupcey

This session will introduce you to Formal Apps; what they are, how they are structured and what is available today.
AutoCheck: Push-Button Bug Hunting

Session - Jun 05, 2015 by Mark Eslinger

This session will show how automation of assertion based methods via automated formal analysis can uncover numerous types of RTL behavioral issues, enabling immediate fixes as the RTL is being developed without the need for a testbench.
Formal-Based Technology

Track - Jun 05, 2015 by Harry Foster

This track introduces basic concepts and terminology that should be useful by any engineer wishing to mature their formal-based technology skills.
Connectivity Check: Connectivity Verification

Session - Jun 05, 2015 by Mark Eslinger

This session we’ll take a quick look at the various challenges in doing connectivity verification with current methods. We’ll also look at a number of connectivity checking applications.
Formal Concepts and Solutions

Session - Jun 05, 2015 by Harry Foster

This session focuses on formal verification concepts and solutions.
Questa AutoCheck

Demo - Jun 05, 2015 by Mark Eslinger

This session will demo the Questa AutoCheck tool and will review features including the details window, design checks window, source, waveform, schematic, and fsm debug features.
Formal Use Models and Organization Skills

Session - Jun 05, 2015 by Harry Foster

This session focuses on formal-based technology use models, and organization guidelines for adopting advanced formal property checking.
Questa Connectivity Check

Demo - Jun 05, 2015 by Mark Eslinger

This session will demo assertions and results and a quick debug showing the QFL waveforms using Questa® Connectivity Check.
CoverCheck: Accelerating Coverage Closure

Session - Jun 05, 2015 by Mark Eslinger

This session will show how automated formal techniques can be used to keep the project moving forward by exhaustively determining the reachability or unreachability of coverage elements, grant persistent waivers to areas that can be safely excluded, and how the master coverage database can be automatically updated with the current coverage score.
Formal Assertion-Based Verification

Track - Jun 05, 2015 by Mark Eslinger

In this track, you will learn how to get started with direct property checking including: test planning for formal, SVA coding tricks that get the most out of the formal analysis engines.
Questa CoverCheck

Demo - Jun 05, 2015 by Mark Eslinger

This session will demo the Questa CoverCheck tool and will review features including the details window, coverage checks window, and source debug features.
Register Check: Memory Mapped Register Verification

Session - Jun 05, 2015 by Mark Eslinger

In this session we’ll take a quick overview of memory mapped verification and some of the challenges users face with verifying these design constructs.
Introduction to Formal Assertion-Based Verification

Session - Jun 05, 2015 by Joe Hupcey

In this session we will learn about various formal verification techniques; what they are, how to utilize them, and benefits received from advanced formal technologies.
Formal Assertion-Based Verification Introduction & Overview

Resource (Slides (.PDF)) - Jun 05, 2015 by Mark Eslinger
Questa Register Check

Demo - Jun 05, 2015 by Mark Eslinger

This session will demo memory mapped register checkers generated results that can be debugged in the using Questa Register Check.
Formal Model Checking

Session - Jun 05, 2015 by Mark Eslinger

In this session we'll share some basic tips for getting started with direct property checking, how to setup the analysis for rapidly reaching a solution, and how to answer the question, “Do I have enough assertions?"
Basic Formal Closure, (Black Boxing and Cutpoint)

Resource (Slides (.PDF)) - Jun 05, 2015 by Mark Eslinger
Basic Formal Closure (Black Boxing and Cutpoint)

Session - Jun 05, 2015 by Mark Eslinger

At some point formal engines will begin to struggle under the weight of the state space. This session will show two simple techniques to safely limit the states the engines need to process, enabling more in-depth results.
Formal Model Checking

Resource (Slides (.PDF)) - Jun 05, 2015 by Mark Eslinger

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Article - Jun 06, 2015 by Neil Johnson

Article - Jun 06, 2015 by Dr. Lauro Rizzatti - Rizzatti LLC

Article - Jun 06, 2015 by Lior Grinzaig - Marvell

Article - Jun 06, 2015 by David Kaushinsky - Siemens EDA

Article - Jun 06, 2015 by Amit Tanwar, Manoj Manu - Siemens EDA

Track - Jun 05, 2015 by Mark Eslinger

Session - Jun 05, 2015 by Joe Hupcey

Session - Jun 05, 2015 by Mark Eslinger

Track - Jun 05, 2015 by Harry Foster

Session - Jun 05, 2015 by Mark Eslinger

Session - Jun 05, 2015 by Harry Foster

Demo - Jun 05, 2015 by Mark Eslinger

Session - Jun 05, 2015 by Harry Foster

Demo - Jun 05, 2015 by Mark Eslinger

Session - Jun 05, 2015 by Mark Eslinger

Track - Jun 05, 2015 by Mark Eslinger

Demo - Jun 05, 2015 by Mark Eslinger

Session - Jun 05, 2015 by Mark Eslinger

Session - Jun 05, 2015 by Joe Hupcey

Resource (Slides (.PDF)) - Jun 05, 2015 by Mark Eslinger

Demo - Jun 05, 2015 by Mark Eslinger

Session - Jun 05, 2015 by Mark Eslinger

Resource (Slides (.PDF)) - Jun 05, 2015 by Mark Eslinger

Session - Jun 05, 2015 by Mark Eslinger

Resource (Slides (.PDF)) - Jun 05, 2015 by Mark Eslinger