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2055 Results

  • Dual Domain Hierarchy Pattern

    The Dual Domain Hierarchy Pattern is an Environment Pattern to facilitate the design of testbenches that can be used for simulation as well as emulation, and across verification engines (or platforms) in general.

  • Verification Patterns - Taking Reuse to the Next Level

    What is a pattern? In the process of designing something (e.g., a building, software program, or an airplane) the designer often makes numerous decisions about how to solve specific problems. If the designer can identify common factors contributing to the derived solution and abstracts the solution in such a way that it can be applied to other similar recurring problems, then the resulting generalized problem-solution pair is known as a pattern.

  • Precedence Chain Property

    The Precedence Chain Property Pattern is used to specify portions of a design model’s execution for relationships between chains (i.e., sequence of states or events1), where an occurrence of a cause chain must be have been preceded by an occurrence of an effect chain. We say that an occurrence of the effect chain is enabled by an occurrence of the cause chain.

  • Response Chain Property

    The Response Chain Property Pattern is used to specify portions of a design model’s execution for relationships between chains (i.e., sequence of states or events), where an occurrence of the cause chain must be followed by an occurrence of the effect chain.

  • Response Property

    The Response Property Pattern is used to specify portions of a design model’s execution for cause-effect relationships between a pair of states or events. An occurrence of the first, the cause, must be followed by an occurrence of the second, the effect . Also known as Follows and Leads -to.

  • Precedence Property

    The Precedence Property Pattern is used to specify portions of a design model’s execution for relationships between a pair of states or events,1 where the occurrence of the first is a necessary pre-condition for an occurrence of the second. We say that an occurrence of the second is enabled by an occurrence of the first.

  • Universality Property

    The Universality Property Pattern is used to specify portions of a design model’s verification execution that contains states or events that have a desired property. Also known as Henceforth   and   Always .

  • Bounded Existence Property

    The Bounded Existence Property Pattern is used to specify portions of a model’s verification execution that contains at most a specified number of instances of designated state transitions or events.

  • Existence Property

    The Existence Property Pattern is used to specify portions of a design model’s verification execution that contains an instance of a certain state or event1. Also known as Eventually or Future .

  • Absence Property

    The Absence Property Pattern is used to specify portions of a design model’s verification execution where a specific state or event1 should never occur. Also known Never .

  • Layering Sequence

    The layering sequence pattern is applicable to any situation where sequences are available that use one sequence_item but must transformed to another sequence_item to be executed on a target sequencer.

  • Utility

    Encapsulate small, useful functionality in a portable, easy-to-use object.

  • Façade

    A façade pattern provides a simple interface to a complex system, making it easier for the client or external world to use.

  • BFM-Proxy Pair

    The BFM-Proxy Pair Pattern is an Environment Pattern to facilitate the design of transactors like drivers and monitors for dual domain partitioned testbenches that can be used for both simulation and emulation, and across verification engines (or platforms) in general.

  • Verification IP Stimulus APIs - Are They Really Easy to Use?

    With the increasing complexity of system designs, there is a pressing need for standalone, pre-verified, built-in verification infrastructures. Verification IP (VIP) is an integral and important component of these infrastructures for block and system-level verification as they reduce cycles spent in verifying complex designs.ly Easy to Use?

  • Verification IP Stimulus APIs - Are They Really Easy to Use?

    Stimulus generation is an important aspect of verification for creating both simple and complex scenarios used to hit functional bugs in a design. Stimulus generation application program interfaces (API) in VIP help you write stimulus without much protocol knowledge and help them create complex protocol scenarios for testing.

  • Patterns Library

    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

  • Leveraging Verification IP (VIP) for Fast & Efficient Verification

    In this session you will learn how Verification IP (VIP) helps to overcome IP verification challenges.

  • UVM Framework – Create a UVM Environment in Less than an Hour

    In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.

  • Leveraging Verification IP (VIP) for Fast & Efficient Verification

    In this session you will learn how Verification IP (VIP) helps to overcome IP verification challenges.

  • UVM Framework – Create a UVM Environment in Less than an Hour

    In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.

  • Technical Paper: A New Stimulus Model for CPU Instruction Sets

  • UVM Forum - All Slides

  • UVM Forum Seminar - 2015: UVM Enabled Advanced Storage IP Silicon Success

  • UVM and Emulation - Easing the Path to Advanced Verification and Analysi