Search Results
Filters
Advanced Search
1983 Results
-
Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis
Paper - Feb 28, 2016 by Avidan Efody
This paper deals with transient fault analysis towards ISO 26262 certification. First we suggest a way to estimate ISO 26262 required metrics with a user specified level of accuracy using statistical sampling of transient faults. We then propose a technique that reuses existing regression results in order to minimize the resources required to analyze faults in both combinatorial and sequential elements.
-
Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis
Resource (Technical Paper) - Feb 28, 2016 by Avidan Efody
Abstract-Shrinking nodes and reduced supply voltages make transient faults due to electromagnetic interferences a growing concern for mission critical ASICs and FPGAs. To address this risk, the ISO 26262 safety automotive standard requires that the impacts of transient faults on safety goals are rigorously analyzed[1]. Such analysis is far from trivial, first and foremost due to the practically infinite number of fault and state combinations that could happen in a component’s life cycle.
-
The Downside of Advanced Verification
Session - Feb 22, 2016 by Neil Johnson
After more than a decade, it’s become obvious the advanced verification techniques we rely on, like constrained random verification, have fallen short of their potential.
-
Introduction to SVUnit
Session - Feb 22, 2016 by Neil Johnson
A history of SVUnit and how it helps to directly address the poor code quality and code debug (redo) currently plaguing semiconductor teams.
-
Your First Unit Test!
Session - Feb 22, 2016 by Neil Johnson
See how easy it is to get started with SVUnit. Generate a unit test template, write unit tests and run them all in less than 20 minutes!
-
Unit Testing UVM Components
Session - Feb 22, 2016 by Neil Johnson
The ability to test UVM components is a key feature of SVUnit. We’ll generate a UVM specific unit test template, add some TLM connectivity and write a unit test to verify a simple UVM model.
-
An Introduction to Unit Testing with SVUnit
Track - Feb 22, 2016 by Neil Johnson
SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is the only SystemVerilog test framework suited for both design and verification engineers.
-
SVUnit Case Studies & Summary
Session - Feb 22, 2016 by Neil Johnson
SVUnit is being used by design and verification engineers to improve bug rates and write high quality code. We’ll look at case studies that support the use of SVUnit and summarize the case for unit testing.
-
Verification with Multi-core Parallel Simulations: Have You Found Your Sweet Spot Yet?
Resource (Poster Paper) - Feb 21, 2016 by Rohit Jain
This poster paper illustrates design types and applications that are suitable and not suitable for multi-core simulations.
-
Verification with Multi-core Parallel Simulations: Have You Found Your Sweet Spot Yet?
Resource (Technical Paper) - Feb 21, 2016 by Rohit Jain
This paper is aimed at verification engineers looking to improve the productivity of their verification flow and to understand where multi-core simulations can provide maximum benefit. Successful multi-core parallel simulations depend on a variety of related design factors, which can be difficult to understand and sort out. With suitable design applications, it is possible to significantly save verification cycles.
-
Forbidden Sequence Property
Resource (Pattern) - Feb 12, 2016 by Harry Foster
The Forbidden Sequence Property Pattern is used to specify portions of a design model’s verification execution that forbids a specified sequence of designated states or events.
-
Resource Sharing
Resource (Pattern) - Feb 12, 2016 by Harry Foster
The Resource Sharing Pattern is used to share resources between objects without requiring detailed knowledge of the resource. Related resources share common access attributes thereby creating simple associations.
-
BFM Notification
Resource (Pattern) - Feb 12, 2016 by Harry Foster
The BFM Notification Pattern is an Analysis Pattern to facilitate the design of transactors for dual domain partitioned testbenches that provide effective and efficient notifications of protocol transaction occurrences, and any other interesting protocol and design events and conditions, for testbench control and analysis.
-
Environment Layering
Resource (Pattern) - Feb 12, 2016 by Harry Foster
The Environment Layering Pattern is used to provide consistent configuration and structure for vertical reuse of environments.
-
Component Configuration
Resource (Pattern) - Feb 12, 2016 by Harry Foster
The Component Configuration Pattern is used to create a coherent configuration structure for the component hierarchy from top to bottom. It promotes self-containment and data-hiding techniques in the configuration and creation of component hierarchy.
-
Dual Domain Hierarchy Pattern
Resource (Pattern) - Feb 12, 2016 by Harry Foster
The Dual Domain Hierarchy Pattern is an Environment Pattern to facilitate the design of testbenches that can be used for simulation as well as emulation, and across verification engines (or platforms) in general.
-
Verification Patterns - Taking Reuse to the Next Level
Resource (Technical Paper) - Jan 22, 2016 by Harry Foster
What is a pattern? In the process of designing something (e.g., a building, software program, or an airplane) the designer often makes numerous decisions about how to solve specific problems. If the designer can identify common factors contributing to the derived solution and abstracts the solution in such a way that it can be applied to other similar recurring problems, then the resulting generalized problem-solution pair is known as a pattern.
-
Precedence Chain Property
Resource (Pattern) - Dec 22, 2015 by Harry Foster
The Precedence Chain Property Pattern is used to specify portions of a design model’s execution for relationships between chains (i.e., sequence of states or events1), where an occurrence of a cause chain must be have been preceded by an occurrence of an effect chain. We say that an occurrence of the effect chain is enabled by an occurrence of the cause chain.
-
Response Chain Property
Resource (Pattern) - Dec 22, 2015 by Harry Foster
The Response Chain Property Pattern is used to specify portions of a design model’s execution for relationships between chains (i.e., sequence of states or events), where an occurrence of the cause chain must be followed by an occurrence of the effect chain.
-
Response Property
Resource (Pattern) - Dec 21, 2015 by Harry Foster
The Response Property Pattern is used to specify portions of a design model’s execution for cause-effect relationships between a pair of states or events. An occurrence of the first, the cause, must be followed by an occurrence of the second, the effect . Also known as Follows and Leads -to.
-
Precedence Property
Resource (Pattern) - Dec 21, 2015 by Harry Foster
The Precedence Property Pattern is used to specify portions of a design model’s execution for relationships between a pair of states or events,1 where the occurrence of the first is a necessary pre-condition for an occurrence of the second. We say that an occurrence of the second is enabled by an occurrence of the first.
-
Universality Property
Resource (Pattern) - Dec 21, 2015 by Harry Foster
The Universality Property Pattern is used to specify portions of a design model’s verification execution that contains states or events that have a desired property. Also known as Henceforth and Always .
-
Bounded Existence Property
Resource (Pattern) - Dec 21, 2015 by Harry Foster
The Bounded Existence Property Pattern is used to specify portions of a model’s verification execution that contains at most a specified number of instances of designated state transitions or events.
-
Existence Property
Resource (Pattern) - Dec 21, 2015 by Harry Foster
The Existence Property Pattern is used to specify portions of a design model’s verification execution that contains an instance of a certain state or event1. Also known as Eventually or Future .
-
Absence Property
Resource (Pattern) - Dec 18, 2015 by Harry Foster
The Absence Property Pattern is used to specify portions of a design model’s verification execution where a specific state or event1 should never occur. Also known Never .