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1983 Results

  • What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

    In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.

  • How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration

    In this session, you will learn how to shorten your formal debug time and how using formal to explore design functionality.

  • Questa Verification IP Configurator

    In this session you learn how Questa Verification IP configurator can be used not only to instantiate and configure Questa VIP components, but also to generate a complete testbench that can be used stand-alone, or integrated into a larger UVM or UVM Framework (UVMF) based environment.

  • Questa Verification IP PCIe®

    In this session you will receive a brief overview of PCI Express® and then learn about the comprehensive functionality Questa Verification IP provides for verification of both IP and SoCs that include a PCIe interface.

  • Questa Verification IP AMBA

    In this session, you will learn about Arm AMBA bus interface protocols as well as learn about the comprehensive functionality Questa Verification IP provides for verification of both IP and SoCs that include an AMBA interface, such as AHB, AXI or ACE.

  • FPGA Prototyping: Maximize Your Enterprise Debug Productivity

    In this session, you will learn how to maximize your enterprise debug productivity.

  • Industry Trends in Today’s Functional Verification Landscape

    In this session, you will learn more about today's industry trends in the functional verification landscape including static and dynamic verification.

  • Enterprise Verification Debug and Analysis

    In this session, you will learn how debug and analysis fits into a platform-based verification solution.

  • System Level Debug & Analysis

    In this session you will learn why block level methods don't work for system level verification and why design bugs commonly escape all the way to the prototyping lab and the debug technology alternatives available to address them.

  • Enterprise Debug for Formal

    In this session you learn more about formal-centric enterprise debug.

  • Enterprise Debug for Simulation

    In this session, you will learn more about common debug challenges and modern debug solutions.

  • Productive Verification with VIP, a UVM Framework and Configuration GUI

    In this session, you will learn how to leverage Verification IP and the UVM Framework to create a running testbench without writing any SystemVerilog code.

  • INs and OUTs of CAN Verification—A Comprehensive UVM-based Solution

  • USB Type-C Verification: Challenges and Solution

  • How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology

  • 24x7 Productivity: Veloce® Enterprise Server App Does the Job

    The way companies use hardware emulation has changed. Historically, emulators were used in a lab, at one location, executing one job at a time. Because of this, an emulator often sat idle. In this scenario, project scheduling for the emulator was done manually by allocating fixed time slots to project teams. An inherently inflexible and inefficient way to manage a valuable resource, especially for global teams.

  • Power Aware Libraries: Standardization and Requirements for Questa Power Aware

    Multi-voltage (MV) based power-ware (PA) design verification and implementation methodologies require special power management attributes in libraries for standard, MV and Macro cells for two distinctive reasons.

  • Improving Performance and Verification of a System Through an Intelligent Testbench

    The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step closer towards achieving more confidence in design with minimal engineering effort. Applications today demand diverse functionality, which results in complex to very complex designs.

  • Functional Verification Study - 2016

    In this session, Harry Foster highlights the key findings from the 2016 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

  • Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces

    With the majority of designs today containing one or more embedded processors, the verification landscape is transforming as more companies grapple with the limitations of traditional verification tools. Comprehensive verification of multi-core SoCs cannot be accomplished without including the software that will run on the hardware. Emulation has the speed and capacity to do this before the investment is made in prototypes or silicon.

  • Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy

    In this session we will deliver five steps your team can take to improve first pass success, and how Questa enables your advanced verification goals every step of the way.

  • Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

    In this paper, we begin by discussing the low power challenges for CDC design and verification including dynamic frequency and voltage scaling (DVFS). The following section describes the low power CDC verification methods and how these methods address the low power issues. Finally, we review some application examples for low power DVFS CDC verification.

  • Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

    With the advances in low power design, new low power artifacts have been introduced that cannot be detected with traditional verification techniques and may cause clock domain crossing (CDC) issues in silicon. This paper explains the new low power CDC issues and the CDC and voltage domain crossing (VDC) verification techniques developed to verify low power designs.

  • Extending a Traditional VIP to Solve PHY Verification Challenges

  • Beyond UVM Registers - Better, Faster, Smarter

    The UVM Register package has many features. These features include reading and writing register values, reading and writing register fields and register blocks. The register model keeps track of the expected value and can directly access the actual modeled register using "back-door access". Using the register model allows a testbench to be written that can check the behavior of registers and address maps.