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2055 Results
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Emerging Trends in AMS Verification Methodology for Automotive & IoT Devices
Resource (Slides (.PDF)) - Jul 20, 2017 by
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Breaking the Speed Limits of SoC Verification
Resource (Slides (.PDF)) - Jul 20, 2017 by Gordon Allan
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Applying Big Data Analytics to Today’s Functional Verification Challenge
Resource (Slides (.PDF)) - Jul 20, 2017 by Harry Foster
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DAC 2017 Academy PDF Presentation: C'mon ... Quit Screwing-Up the UVM $display Command!!
Resource - Jul 20, 2017 by
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Add Unit Testing To Your Verification Tool Belt
Resource (Slides (.PDF)) - Jul 20, 2017 by Neil Johnson
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SystemVerilog Object Oriented Programming Basics used in UVM Verification
Resource (Slides (.PDF)) - Jul 20, 2017 by
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SystemVerilog OOP Basics used in UVM Verification
Webinar - Jul 12, 2017 by Dave Rich
In this session, you will learn some of the core concepts behind Object-Oriented Programming to help you get a better understand what a methodology like the UVM can do for you.
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Parallel Debug: A Path to a Better Big Data Diaspora
Article - Jun 28, 2017 by Hamilton Carter - Siemens EDA
This article describes a methodology—parallel debug—as well as a supporting Jenkins framework, enabled by the availability of massive processor and disc farms which are commonplace among chip design projects. Parallel debug is an objective, disciplined methodology wherein the engineer changes one and only one aspect of a complex problem based on a hypothesis, and then tests the hypothesis. That is to say, it's the scientific method repackaged as a debug technique.
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Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow
Article - Jun 28, 2017 by Mike Andrews, Mike Fingeroff - Siemens EDA
Portable Stimulus has become quite the buzz-word in the verification community in the last year or two, but like most 'new' concepts it has evolved from some already established tools and methodologies. For example, having a common stimulus model between different levels of design abstraction has been possible for many years with graph-based stimulus automation tools like Questa inFact.
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Smoothing the Path to Software-Driven Verification with Portable Stimulus
Article - Jun 28, 2017 by Matthew Ballance
Designs are becoming more complex and increasingly include a processor – and often multiple processors. Because the processor is an integral part of the design, it's important to verify the interactions between software running on the processor and the rest of the design.
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Verification Planning with Questa Verification Management
Article - Jun 28, 2017 by Darron May
Verification of complex SoC (System on Chip) requires tracking of all low-level data (i.e. regression results, functional and code coverage). Usually, verification engineers do this type of tracking manually or using some automation through scripting. Manual efforts in order to get above information while verifying complex SoC may lead us towards the delay in project execution.
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MIPI® CSI2 TX IP Verification Using Questa Verification IPs
Article - Jun 28, 2017 by Ivan Ristic
The purpose of this article is to present the verification process of HDL Design House MIPI® CSI2 TX IP core using Questa Verification IPs by Siemens EDA.
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Converting Legacy USB IP to a Low Power USB IP
Article - Jun 28, 2017 by Anand Paralkar, Pervez Bharucha - Silicon Interfaces
Two common queries that customers pose to a design house is whether an existing or new IP can be made "low power" or if "power aware" verification can be carried out on an IP. The IEEE standard – P1801 captures what one may call the syntax and semantics to express the intent of the power architecture of a design.
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Understanding the UPF Power Domain and Domain Boundary
Article - Jun 28, 2017 by Progyna Khondkar
The Unified Power Format (UPF) plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. A higher process node is definitely attractive as more functionality integration is possible in a smaller die area at a lower cost.
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Automation and Reuse in RISC-V Verification Flow
Article - Jun 28, 2017 by Marcela Zachariasova, Lubos Moravec - Codasip, Ltd.
The Open RISC-V Instruction Set Architecture (ISA) managed by the RISC-V foundation 1 and backed by an ever increasing number of the who's who in the semiconductor and systems world, provides an alternative to legacy proprietary ISA's. It delivers a high level of flexibility to allow development of very effective application optimized processors, which are targeted to domains that require high performance, low area or low power.
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Emulation - A Job Management Strategy to Maximize Use
Article - Jun 28, 2017 by Vijay Chobisa
There are many reasons why hardware-based emulation is a “must have” for an effective verification flow. Increased complexity, protocols, embedded software, power and verification at the system level all drive the need for the kind of performance, capacity, and “shift-left” methodology that only emulation delivers.
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RTL CDC is No Longer Enough: How Gate-Level CDC is Now Essential to First Pass Success
Article - Jun 28, 2017 by Joe Hupcey
Clock-domain crossing (CDC) verification is a critical step in the design verification cycle. However, CDC verification is not only necessary on RTL; at 28nm nodes and below it is also essential on gate-level designs due to the possibility of the introduction of CDC errors during the synthesis phase that can lead to silicon failure. In this article we review the root cause of these challenges and introduce an automated approach to overcome these difficulties.
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Formal Verification: Not Just for Control Paths
Article - Jun 28, 2017 by Rusty Stuber - Siemens EDA
Formal property verification is sometimes considered a niche methodology ideal for control path applications. However, with a solid methodology base and upfront planning, the benefits of formal property verification, such as full path confidence and requirements based property definition, can also be leveraged for protocol driven datapaths.
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Migrating to UVM 1800.2
Chapter - Jun 24, 2017 by Verification Methodology Team
The UVM became the IEEE Standard for Universal Verification Methodology Language Reference Manual - 1800.2 in 2017
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UVM Debug
Track - Jun 14, 2017 by Tom Kiley
In this track, we examine common UVM debug issues, and provide a systematic set of recommendations to effectively address them.
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UVM Debug Editor Insight
Resource (Slides (.PDF)) - Jun 14, 2017 by Harry Foster
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UVM Debug Editor Insight
Session - Jun 14, 2017 by Harry Foster
This editor insight session provides an historical perspective on the origin of the word debugging, followed by a discussion on industry trends that motivated us to create the UVM debug track.
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UVM Connectivity Debug
Session - Jun 14, 2017 by Tom Kiley
In this session we will discuss how to debug connectivity issues between UVM components using the UVM Schematic viewer.
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UVM Connectivity Debug
Resource (Slides (.PDF)) - Jun 14, 2017 by Tom Kiley
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UVM Phase Debug
Session - Jun 14, 2017 by Tom Kiley
In this session we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.