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2075 Results

  • Coverage & Plan-Driven Verification for FPGAs

    This session explores how to ensure that debug and verification is done in the most effective place by using block benches, chip benches, formal tools, and lab test appropriately.

  • Questa Clock-Domain Crossing

    Questa CDC addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques.

  • Visualizer: Livesim / Interactive

    In this track, you will learn how Visualizer Debug Environment provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

  • Automatic X Tracing in Your Design

    In this session we will discuss how to trace the source of the problem using Visualizer Time Cone view.

  • Wave Windows Features

    In this session, we will review the wave window features and and how you can leverage them in your debug activity.

  • FSM Viewer

    In this session we show how to debug FSM issues efficiently in Visualizer.

  • Driver and Receiving Tracing

    In this session we will discuss how Visualizer enables you to quickly trace drivers and receivers.

  • Design Exploration with the Advanced Search Window

    In this session, you will learn how to explore or search for objects in your design (memory, packages etc…) in Visualizer.

  • Adding Signals to the Wave Window

    In this session we will discuss the many ways you can add signals to the wave window in Visualizer.

  • Invoking Visualizer

    In this session, you will learn how to generate the design.bin file and invoke Visualizer in interactive mode.

  • Commonly Used Windows

    In this session, you will be introduced to the most common window layouts in Visualizer interactive debug.

  • Set Breakpoints and Single Step Debug

    In this session you will learn how to use breakpoints in the testbench and single step debug.

  • Viewing Data Values

    In this session, you will learn how to look for Values, browse, add to watchlist, VA & VT, add to local window.

  • Navigating a UVM Testbench

    In this session, you will learn how to navigate the testbench using UVM based hierarchy, sequence, threads and class instance.

  • Navigation with Class and File Views

    In this session, you will learn how to navigate the testbench using file, class and lexical search (non UVM).

  • RTL Interactive Debug

    In this session, you will learn how to view RTL data during interactive debug.

  • Checkpoint/Restore

    In this session, you will learn how to utilize checkpoint/restore during interactive debug.

  • Visualizer Tutorials: BreakPoint & UVM Interactive

  • Visualizer Tutorials: UVM Interactive

  • Visualizer Tutorials: UVM Interactive Lab

  • Visualizer Tutorials: Source Code

  • Visualizer Tutorials: Breakpoint

  • Visualizer Tutorials: Breakpoint Lab

  • Formal Coverage

    Formal coverage is a hot topic these days. Simulation has a number of metrics for helping determine when verification is done. These include code coverage, assertions coverage, transaction coverage, and functional coverage to name a few.

  • Formal Coverage Introduction & Overview

    In this session, you will be introduced to the Formal Coverage track and its sessions including; simulation coverage, property debug, resolving inconclusives and over-constraint & reachability analysis.