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Questa VIP Integration

Resource (Slides (.PDF)) - Mar 04, 2018 by Dave Aerne
UVMF & Emulation

Session - Mar 04, 2018 by Mike Horn

The UVMF works out of the box with both simulators and emulators, but how? This session helps you to understand Testbench Acceleration and how the UVMF gets you there.
Configuring Memory Read Completions Sent by PCIe® QVIP

Article - Mar 01, 2018 by Arushi Jain, Rajat Rastogi - Siemens EDA

In real hardware systems, the read completion sizes for upstream read requests (initiated towards the root complex) are characteristics of the processor in use and the maximum payload size (request payload size) limitations of endpoint as a receiver. Out of various aspects to be considered while creating a read completion, important aspects of data associated with it are byte enables (valid data to be read), value of the read request, and address at which the request is initiated.
SATA Specification 3.3 Gaps Filled by SATA QVIP

Article - Mar 01, 2018 by Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens EDA

Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors and mass storage devices. SATA is a high-speed serial protocol with a point-to-point connection between the host and each of its connected devices. It is a layered protocol comprising of a command and application layer, transport layer, link layer, and physical layer.
From Power Intent to Microarchitectural Checks of Low-Power Designs - Part 1

Article - Mar 01, 2018 by Progyna Khondkar

PA-Static verification is primarily targeted to uncover the power aware structural issues that affects designs physically in architectural and microarchitectural aspects. The structural changes that occur in a PA design are mostly due to physical insertions of special power management and MV cells; such as power switches (PSW), isolation (ISO), level shifter (LS), enable level shifter (ELS), repeaters (RPT), and retentions flops (RFF).
A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs

Article - Mar 01, 2018 by Dr. Mike Bartley

This article outlines a hierarchical and configurable verification strategy for RISC-V based IP and SoCs. A three-level (unit, core and SoC) hierarchy is proposed for testbenches. Each level of the hierarchical testbench is configurable for both architectural and micro-architectural parameters. At the heart of the verification strategy is an ISG (Instruction Stream Generator) and a UVM testbench.
SVA Alternative for Complex Assertions

Article - Mar 01, 2018 by Ben Cohen

This article first explains the concepts, and then by example, how a relatively simple assertion can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as vacuity or an error in the assertion, providing examples that demonstrate how some of the SVA limitations can be overcome with the use of tasks, but yet maintain the spirit ( but not vendor’s implementations ) of SVA.
Testbench: Architecture and Operation

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
Testbench: Architecture and Operation

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn about the architecture of a UVMF testbench and directory structure.
Environment Code Generation

Session - Feb 26, 2018 by Jonathan Craft

In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Environment.
Environment Code Generation

Resource (Slides (.PDF)) - Feb 26, 2018 by Jonathan Craft
Scoreboards and Predictors

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn the roles and responsibilities of scoreboards and predictors within the UVMF, the scoreboards provided by UVMF and how they are configured.
Scoreboards and Predictors

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
Environments: Architecture and Operation

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
Environments: Architecture and Operation

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn the roles and responsibilities of an environment within a simulation.
Interface Code Generation

Session - Feb 26, 2018 by Jonathan Craft

In this session, you will learn the steps needed to produce code for an UVMF Interface using the generator.
Interface Code Generation

Resource (Slides (.PDF)) - Feb 26, 2018 by Jonathan Craft
Agents: Architecture and Operation

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
Agents: Architecture and Operation

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn about components within a protocol agent and its associated bus functional models and the roles and responsibilities of these components including the abstraction level they operate at.
Code Generation Introduction

Resource (Slides (.PDF)) - Feb 26, 2018 by Jonathan Craft
Code Generation Introduction

Session - Feb 26, 2018 by Jonathan Craft

In this session, you will learn why code generation can be a powerful tool and how to take advantage of it for the purposes of quickly producing a UVMF-based testbench.
UVMF - Overview

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn what the UVM Framework is, the functionality it provides, its testbench architecture, and available documentation and support.
UVMF - Overview

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
UVMF - Series Introduction

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
UVMF - Series Introduction

Session - Feb 26, 2018 by Bob Oden

In this session, you are introduced to the UVM Framework and the list of sessions that comprise this video track.