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2055 Results
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SLEC System Flow: Leveraging Formal in Math Primitive Verification Closure
Resource (Slides (.PDF)) - May 01, 2025 by Abhiram Dronavalli - Microsoft
This presentation shows how Microsoft leveraged SLEC System strategies used for convergence.
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Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Resource (Slides (.PDF)) - May 01, 2025 by Benjamin Ting, Linh Nguyen - Microsoft
This presentation describes the development and implementation of a formal-based application flow to successfully address the unique challenges encountered in dynamically retargeting connectivity verification to multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs.
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Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Resource (Recording) - May 01, 2025 by Benjamin Ting, Linh Nguyen - Microsoft
This presentation describes the development and implementation of a formal-based application flow to successfully address the unique challenges encountered in dynamically retargeting connectivity verification to multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs.
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osmosis 2025 - Ask the Experts Panel
Resource (Recording) - May 01, 2025 by Chris Giles
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osmosis 2025
Conference - May 01, 2025 by Nicolae Tusinschi
The annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. The conversations that follow may help you and others improve formal-based verification solutions.
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Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity
Webinar - Apr 30, 2025 by Kevin Ham
This session introduces Avery Verification IP for Ethernet 1.6T, Infiniband, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity. You will gain insights into the key challenges and innovations in Ethernet 1.6T, the latest high-speed Ethernet standard, and learn how Avery's Verification IP accelerates design validation with comprehensive protocol coverage, scalability, and advanced debugging capabilities.
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Breaking Barriers: Ethernet 1.6T, UALink, and UEC Verification for Next-Gen Connectivity
Resource (Slides (.PDF)) - Apr 30, 2025 by Kevin Ham
This session introduces Avery Verification IP for Ethernet 1.6T, Infiniband, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity.
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Securing your FPGA Design from RTL through to the Bitstream
Webinar - Apr 23, 2025 by Keerthi Devraj
This session will briefly introduce practical tools such as the Siemens Analyze Architecture and VerifySecure technologies, highlighting how they support the overall security strategy. In addition, we will introduce Bitwise (powered by Red Balloon Security) as a point-and-click assurance tool that delivers rapid security analysis and hardening of FPGA bitstreams.
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Securing your FPGA Design from RTL through to the Bitstream
Resource (Slides (.PDF)) - Apr 23, 2025 by Keerthi Devraj
This session will briefly introduce practical tools such as the Siemens Analyze Architecture and VerifySecure technologies, highlighting how they support the overall security strategy.
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Closing the Gap in Software Skills for Verification Engineers
Resource (Verification Horizons Blog) - Apr 17, 2025 by Dave Rich
I’m excited to announce next month’s U2U (User-to-User) meeting , followed by a crucial technical training session that no hardware verification engineer should miss.
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Faster Debug Using QuestaSim Interactive Coverage Analysis
Resource (Slides (.PDF)) - Apr 16, 2025 by Justin Royse
In this webinar, you will learn how interactive coverage analysis brings another dimension to RTL and SV/UMV debugging which can lead to significant productivity boost and faster design and testbench bring up.
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Faster Debug Using QuestaSim Interactive Coverage Analysis
Webinar - Apr 16, 2025 by Justin Royse
This session we will explore the power of debugging code and functional coverage while simulation is still running. Learn how interactive coverage analysis brings another dimension to RTL and SV/UMV debugging which can lead to significant productivity boost and faster design and testbench bring up.
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Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator
Webinar - Apr 03, 2025 by Mark Carey
This session will explore the powerful Smart Debug features within Siemens EDA’s Questa Verification IQ Regression Navigator - a next-generation, collaborative browser-based data-driven verification solution. Leveraging advanced machine learning technology, these features enable you to accelerate root cause analysis and reduce debug turnaround time.
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Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator
Resource (Slides (.PDF)) - Apr 03, 2025 by Mark Carey
This session will explore the powerful Smart Debug features within Siemens EDA’s Questa Verification IQ Regression Navigator - a next-generation, collaborative browser-based data-driven verification solution.
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PCIe Gen7 Verification with Siemens Avery Verification IP
Webinar - Mar 26, 2025 by Zhihong Zeng
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks.
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PCIe Gen7 Verification with Siemens Avery Verification IP
Resource (Slides (.PDF)) - Mar 26, 2025 by Zhihong Zeng
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks.
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Accellera announces fee-free availability of IEEE Std. 1801™-2024
Resource (Verification Horizons Blog) - Mar 19, 2025 by Dennis Brophy
Accellera announced the latest revision of the IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems, also known as the Unified Power Format (UPF) 4.0, has been published by the IEEE. Fee-free access to the standard is provided courtesy of Accellera. It builds upon previous versions to provide a comprehensive framework to design and verify low-power, energy-aware electronic systems.
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Safety Analysis for Automotive Chips Based on ISO 26262
Resource (Slides (.PDF)) - Mar 12, 2025 by Jyothy M Jaganathan
In this webinar, we will be focusing on the usage of SafetyScope at various stages of a safety design cycle: architectural phase, RTL phase and post-synthesis phase.
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Safety Analysis for Automotive Chips Based on ISO 26262
Webinar - Mar 12, 2025 by Jyothy M Jaganathan
In this webinar, we will be focusing on the usage of SafetyScope at various stages of a safety design cycle: architectural phase, RTL phase and post-synthesis phase. We will also demo showing initial FIT calculations as well as the ISO 26262 metrics, what if analysis and exploration to reach ASIL B safety.
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GOMACTech 2025 Preview: Improving Productivity with Parallel Simulation
Resource (Verification Horizons Blog) - Mar 10, 2025 by Joe Hupcey
Field Programmable Gate Arrays (FPGAs) continue to be a critical part of system designs, and their complexity grows as new technology allows for faster and bigger devices. Naturally, this calls for longer RTL-level simulations to allow for more realistic testing scenarios, but the time spent waiting for results often delays discovery of design bugs.
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Faster Debug of Complex Testbenches using Visualizer
Webinar - Mar 05, 2025 by Erik Jessen
In this webinar, we will explore essential capabilities such as basic line stepping, dynamic variable monitoring, constraint debugging, and UVM topology visualization. In addition, you will learn how to effectively identify and resolve issues in complex testbenches, streamline workflows, and enhance overall verification efficiency.
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Faster Debug of Complex Testbenches Using Visualizer
Resource (Slides (.PDF)) - Mar 05, 2025 by Erik Jessen
In this session, you will learn how to effectively identify and resolve issues in complex testbenches, streamline workflows, and enhance overall verification efficiency.
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GOMACTech 2025 Preview: FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking
Resource (Verification Horizons Blog) - Mar 04, 2025 by Joe Hupcey
Security and safety policies across domains such as embedded security, defense safety, and automotive safety have been updated to require the ability to prove that an FPGA design’s functionality is unchanged from RTL through synthesis, P&R, and bitstream generation.
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Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
Resource (Slides (.PDF)) - Feb 19, 2025 by Kevin Urish
In this session, you will learn comprehensive solutions to tackle current and emerging requirements for FPGA designs.
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Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
Webinar - Feb 19, 2025 by Kevin Urish
Security and safety policies across various domains such as aerospace and defense, embedded security, and automotive safety have been updated to require an FPGA verification chain spanning from verified HDL source, extending throughout the FPGA implementation tool chain, and culminating with the FPGA bitstream. In this session, you will learn comprehensive solutions to tackle current and emerging requirements for FPGA designs.