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2073 Results
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Questa CDC Verification
Demo - Sep 14, 2021 by Kurt Takara
This session demonstrates the Questa CDC Verification comprehensive solution to clock-domain verification.
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Python and the UVM
Resource (Verification Horizons Blog) - Sep 09, 2021 by Ray Salemi
An introduction to pyuvm and how we can use it to write UVM code on top of cocotb .
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Questa Reset Domain Crossing (RDC)
Demo - Sep 02, 2021 by Atul Sharma
This session will demonstrate the Questa RDC Verification Solution and will introduce key features in RDC GUI, like RDC Matrix, Directive Window and other debug features.
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What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Article - Sep 01, 2021 by Tom Fitzpatrick
Preface: in May 2021 Siemens EDA acquired OneSpin Solutions, combining Siemens' Questa Formal products and expertise (with roots and team members from 0-In) with OneSpin’s “apps first” approach to key growth markets including Trust&Security, Safety, RISC-V, and FPGAs. The combination adds to a cohesive Siemens EDA verification solution spanning simulation, formal, emulation, and prototyping.
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Digital Thread, Digital Twin, and IC Development
Article - Sep 01, 2021 by Ray Salemi
In October of 2020, the Air Force challenged Aerospace and Defense industry to adopt the suggestions presented in the 2018 Digital Engineering Strategy. The document, named " There is No Spoon: The New Digital Acquisition Reality ”, warns that aircraft design and deployment must embrace “the digital trinity” of Digital Engineering and Management, Agile Software Development, and Open Architecture.
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Addressing the Trends and Challenges of Automotive IC Development
Article - Sep 01, 2021 by Ann Keffer
Developers of ICs, systems, and even vehicles are seeing some pretty significant shifts in the automotive industry. Recent estimates forecast that 50% of a vehicle’s Bill of Materials (BOM) will be electronics and electronic systems by the year 2030. Smart mobility is the root cause as the market demands features such as lane keep, adaptive cruise control, and emergency brake assist to name a few.
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Deploying HLS in a DO-254/ED-80 Workflow
Article - Sep 01, 2021 by Tammy Reeve - Patmos Engineering Services
The adoption of tools into safety-critical workflows is often challenging as these new technologies must demonstrate sufficient safeness to use before being deployed in production environments. The demand for High-Level Synthesis capabilities within DO-254 projects is growing and this paper describes the requirements and considerations to successfully use High-Level Synthesis within a DO-254 workflow.
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Hardware-Assisted Verification Through the Years
Article - Sep 01, 2021 by Jean-Marie Brunet
A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. When combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in hardware. The focus on tools and delivering a tightly woven integration between complementary tools is a strategic focus at Siemens EDA.
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Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive
Article - Sep 01, 2021 by Jean-Marie Brunet
Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof. According to market research International Business Strategies (IBS), the total cost of designing a state-of-the-art system on chip (SoC) at the 5nm process technology node exceeds half a billion dollars.
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Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs
Article - Sep 01, 2021 by Stephen Bailey
In a 2010 inaugural issue of the report from the UK High Performance Computing Special Interest Group (HPC-SIG), the following statement resonated with a large number of companies and research institutions that were using HPC technology. "Over the past decade there has been a revolution in High Performance Computing spearheaded by a movement away from using expensive traditional proprietary supercomputers to systems based on relatively inexpensive commodity off-the-shelf systems." [1]
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"Hug the Debug" – Before It’s Too Late
Article - Sep 01, 2021 by Sumit Vishwakarma
Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by the global chip shortage, especially in the automotive industry.
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Questa Visualizer Adds Coverage Analysis to the Platform
Article - Sep 01, 2021 by Yara Esam - Siemens EDA
Questa Visualizer Debug is our high performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs.
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Verifying a DDR5 Memory Subsystem
Article - Sep 01, 2021 by Kamlesh Mulchandani
The latest technologies and applications often demand more speed and performance. With the advancement in technologies such as multi-core CPUs and GPUs, the need for faster data processing is becoming a bottleneck for system performance. Applications such as Machine Learning and Data Centers rely upon high performance and lower latency. These applications need a memory that can offer high speed, better performance, high density, lower latency, and data integrity.
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Expediting Simulation Turn-around Time with Incremental Build Flow
Article - Sep 01, 2021 by Neil Johnson
Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use to constantly validate progress. Whether the result is a failed compile, passing simulation or anything in between, the sooner you get that result, the sooner you get to the next step and closer you get to your ultimate objective: passing silicon.
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Standards Participation at Siemens EDA
Article - Sep 01, 2021 by Dave Rich
All of us are involved with standards every day whether we realize it or not. From the day we are born, we interact with standards. In the US, a baby receives a standardized health assessment score called Apgar after 1 minute. You are weighed and measured to standards. You wear clothes sized to standards. Eventually, you learn to read and write according to some culturally accepted standards.
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IP Security: Keys to Early Identification of Security Vulnerabilities
Webinar - Aug 27, 2021 by John Hallman
In this session we will demonstrate early security verification on a small module of intellectual property (IP) intended for integration into an IC. Using Methodics IPLM by Perforce’s key technology for IP management and OneSpin 360™ formal verification tools, our technical experts will jointly perform the process recently released for public comment in the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard.
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UVM Connect 2.3 Primer
Resource (Reference Documentation) - Aug 25, 2021 by John Stickley
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RDC Overview & Questa RDC Methodology
Webinar - Aug 21, 2021 by Atul Sharma
In this session, you will learn more about Reset Domain Crossing problems and methods to address it. Then you will be introduced to the Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR.
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RDC Overview & Questa RDC Methodology
Resource (Slides (.PDF)) - Aug 21, 2021 by Atul Sharma
In this session, you will learn more about Reset Domain Crossing problems and methods to address it. Then you will be introduced to the Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR.
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Should I Kill My Formal Run? Part 1: Formal Run is In-Progress
Webinar - Aug 20, 2021 by Dr. Jeremy Levitt
In this session we will show you the information you can use to decide whether to continue or stop the formal job such as how to monitor the formal engines’ “health” in real time and why a given property analysis might be getting stuck.
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Exploration into Safety Analysis Techniques That Optimize the Safety Workflow
Webinar - Aug 13, 2021 by Ann Keffer
In this session, you will gain an understanding of how Siemens EDA provides a methodology that results in achieving a single iteration around costly fault injection, resulting in a more predictable project schedule and an accelerated time-to-certification.
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UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level
Webinar - Aug 05, 2021 by Pedram Riahi - Raytheon
This session is a customer presentation on his experience using the UVMF and Mathworks® integration in block, subsystem, and chip level simulations.
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Deploying Formal in a DO-254 Program
Resource (Verification Horizons Blog) - Aug 02, 2021 by Jake Wiltgen
The primary focus of DO-254, referred to as ED-80 in Europe, is hardware reliability of airborne electronic hardware. DO-254 is considered state of the art and compliance is compulsory for any company putting an IC on an aircraft. One component of the standard is the verification of functional behavior.
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Managing Requirements in a Functional Safety Environment
Webinar - Jul 29, 2021 by Thorsten Stahlberg - Siemens EDA
In this session, you will learn that Requirements Management in a "Functional Safety" environment can be very challenging. With Polarion ALM you have a comprehensive solution at hand that fully supports you in successfully managing not only the pure requirements themselves but also all related processes.
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Using Formal Verification in Daily Work
Webinar - Jul 29, 2021 by Dr. Abdelouahab Ayari - Siemens EDA
In this session, we will describe some typical formal applications and how the formal results can be integrated with other verification results.