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Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

Resource (Slides (.PDF)) - Feb 18, 2026 by Jalaj Gupta

PCIe® Gen7 delivers unprecedented bandwidth and introduces stronger security capabilities, including TDISP for device security and isolation, and IDE for end-to-end data encryption and integrity.
Beyond Simulation: Unlocking Absolute Certainty in Hardware Design with Formal Verification

Resource (Verification Horizons Blog) - Feb 16, 2026 by Nicolae Tusinschi

Have you ever wondered how we can truly guarantee that the complex chips powering our world – from smartphones to self-driving cars – will always work flawlessly, even in the most obscure scenarios? It’s a question that keeps many engineers up at night, especially as designs grow exponentially more intricate. That’s precisely the challenge addressed in my recent paper, Achieving Mathematical Certainty in Design Verification with Formal .
Future-Proof Your Designs: The Power of Verify Property in Digital Verification

Webinar - Feb 12, 2026 by Bobana Brzacki

This webinar reveals cutting-edge tools that empower engineers to identify complex structural issues, connectivity errors, and X-propagation problems early in the design cycle without stimulus generation. Learn how to streamline your verification workflow, accelerate time-to-market, and deliver robust, high-quality designs while significantly reducing costly re-spins and debug cycles.
Future-Proof Your Designs: The Power of Verify Property in Digital Verification

Resource (Slides (.PDF)) - Feb 12, 2026 by Bobana Brzacki

Learn how to streamline your verification workflow, accelerate time-to-market, and deliver robust, high-quality designs while significantly reducing costly re-spins and debug cycles.
Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

Resource (Slides (.PDF)) - Feb 11, 2026 by Kurt Takara

In this webinar, you will learn how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and filter functionally false positives.
Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

Webinar - Feb 11, 2026 by Kurt Takara

This webinar will discuss how Questa CDC Power Aware analysis can address this problem, as well as describe how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and filter functionally false positives.
Close Coverage Faster with Questa One Sim's Unreachability Analysis

Webinar - Feb 05, 2026 by Justin Royse

Coverage closure remains the single largest challenge facing functional verification teams today, affecting 34% of both ASIC and FPGA design projects. As verification approaches completion, coverage scores plateau well short of project goals—a phenomenon commonly known as the "Last Mile problem." This webinar explores why traditional approaches to closing coverage gaps fall short and introduces  automated unreachability analysis  in Questa One Sim as a transformative solution.
Close Coverage Faster with Questa One Sim's Unreachability Analysis

Resource (Slides (.PDF)) - Feb 05, 2026 by Justin Royse

This webinar explores why traditional approaches to closing coverage gaps fall short and introduces  automated unreachability analysis  in Questa One Sim as a transformative solution.
Compute Subsystem RTL Signoff with CSS VIP and Software Aware VIP

Resource (Slides (.PDF)) - Feb 04, 2026 by Luis Rodriguez

This session highlights a robust methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 based and also RISC-V based Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models. Guest Presenter: Purna Mohanty – Signature IP
Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

Resource (Slides (.PDF)) - Feb 04, 2026 by Jalaj Gupta

In this session, you will learn more about Security Verification with Avery PCIe Verification IP and features in Avery PCIe Gen7.
Verifying Chiplet Interconnects at Scale: UCIe® 3.0

Resource (Slides (.PDF)) - Feb 04, 2026 by Luis Rodriguez

This session highlights what’s new in UCIe 3.0 and explains how Avery UCIe Verification IP enables faster bring-up, deeper protocol coverage, and reduced risk by validating compliance, corner cases, and system-level behavior—helping teams confidently deliver robust chiplet-based silicon. Guest Presenter: Jie Ding – Ayar Labs
Verifying Future Accelerator Interconnects: UALink™ Verification IP and Why UALink Matters

Resource (Slides (.PDF)) - Feb 04, 2026 by Jalaj Gupta

This session highlights the importance of UALink and the verification challenges it introduces and shows how Avery UALink Verification IP delivers immediate value by accelerating bring-up, improving coverage of protocol corner cases, and reducing overall verification risk and time-to-market. Guest Presenter: Saro Kalinagasamy – Astera Labs
Achieving Mathematical Certainty in Design Verification with Formal

Paper - Jan 31, 2026 by Nicolae Tusinschi

This paper provides a comprehensive exploration of formal verification methodologies, techniques, and best practices for hardware design engineers and verification specialists. Formal verification employs mathematical analysis to prove correctness across all possible scenarios. This exhaustive approach is particularly critical in safety-critical systems, high-reliability applications, and complex digital designs where corner-case bugs can have catastrophic consequences.
Achieving Mathematical Certainty in Design Verification with Formal

Resource (Paper (.PDF)) - Jan 31, 2026 by Nicolae Tusinschi

The future of hardware verification lies in the intelligent combination of formal verification, simulation, and other verification methodologies, each applied where it provides the most value. By mastering the techniques presented in this whitepaper, verification engineers position themselves to meet the verification challenges of increasingly complex hardware designs.
Cut Weeks From Debug: Rapid First – Level Bug Hunting with Inspect and Check X

Webinar - Jan 29, 2026 by Bobana Brzacki

In this webinar we introduce intuitive 'push-button' bug-hunting tools, Inspect and Check X, designed to transform your verification process. Join us for a practical deep dive into their core functionalities, demonstrating their efficient workflow from initial setup to insightful results analysis. You will gain a clear understanding of how these powerful solutions empower them to rapidly identify and resolve first-level design bugs, ensuring a more robust design and accelerated time-to-market.
Cut Weeks From Debug: Rapid First – Level Bug Hunting with Inspect and Check X

Resource (Slides (.PDF)) - Jan 29, 2026 by Bobana Brzacki

In this webinar, you will gain a clear understanding of how these powerful solutions empower them to rapidly identify and resolve first-level design bugs, ensuring a more robust design and accelerated time-to-market
Supercharge Your CDC & RDC Analysis with the Power of AI/ML

Webinar - Jan 28, 2026 by Farhad Ahmed

One of the biggest challenges in CDC/RDC verification is managing the complexity and time-consuming nature of identifying and resolving violations. CDC/RDC Assist addresses this challenge by leveraging AI/ML to automate and accelerate causality analysis. In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.
Supercharge Your CDC & RDC Analysis with the Power of AI/ML

Resource (Slides (.PDF)) - Jan 28, 2026 by Farhad Ahmed

In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.
Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

Webinar - Jan 21, 2026 by Sunil Sahoo

This webinar will delve into  Questa One Sim’s groundbreaking metastability injection capability , a pivotal advancement that brings the critical aspect of non-deterministic delay validation directly into the simulation realm. We will demonstrate how this new feature enables designers to actively model and inject varying metastability delays into synchronizer paths, allowing for rigorous verification of sequential reconvergence logic.
Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

Resource (Slides (.PDF)) - Jan 21, 2026 by Sunil Sahoo

In this webinar, you will learn how to gain unparalleled confidence in your design’s resilience to metastability effects, ensuring robust functional correctness and accelerating verification closure for complex multi-clock SoCs.
BUGGED OUT Podcast

Podcast - Jan 20, 2026 by Harry Foster

Every chip has bugs — the real question is how fast you can find and fix them. BUGGED OUT is the bite-sized podcast where we shine a light on the art (and science) of functional verification.
New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

Resource (Paper (.PDF)) - Jan 16, 2026 by Jin Hou

The heterogeneous integration of multiple ICs in a single package along with high-performance, high bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making it extremely challenging to verify the correctness of the connections.
New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

Paper - Jan 16, 2026 by Jin Hou

This paper introduces a new way to functionally verify packaging connectivity using formal verification that can exhaustively verify all interconnections between IC blocks. The flow is automatic for all steps, from creating connectivity specifications to verifying packaging output connectivity. The automatic parallel algorithms on the compute grid can verify huge numbers of connections in minutes or even seconds. The script for the flow is simple and only takes a few minutes to set up.
Formal Verification Made Simple: A Practical Guide for FPGA Designers

Webinar - Jan 15, 2026 by Bobana Brzacki

In this webinar we will demystify formal verification and show you how SFV fits naturally into your existing FPGA design flow. Whether you're working on control logic, interfaces, or complex state machines, you'll discover how formal can catch bugs that simulation misses - early, automatically, and exhaustively.
Formal Verification Made Simple: A Practical Guide for FPGA Designers

Resource (Slides (.PDF)) - Jan 15, 2026 by Bobana Brzacki

If you're an FPGA designer who's heard that formal verification is "too complex" or "not for FPGA workflows," this session will change your mind.