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Functional Verification Using Siemens Questa Simulation Technologies
Conference - May 20, 2025 by Nirmala Balakrishnan
Working at the leading edge of AI Computing, with Chiplet architectures, advanced protocol and memory interfaces, it is essential that our IPs, DUTs, and functional Design Verification teams continue to scale up along with our product line and company. In this session, you will learn how Tsavorite Scalable Intelligence harnessed the UVM Framework to automate testbench and make-file infrastructure generation and got them started quickly with QuestaSim regressions.
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Shift Left using AutoCheck Formal Verification
Conference - May 20, 2025 by Mitchell Poplingher
Automated applications with formal verification under-the-hood can truly enable a “shift left”, which will be shown in this presentation on Siemens' Questa AutoCheck. In this case study, we share how this complements our simulation-based RTL verification, as it offers distinct advantages in accelerating bug detection during early RTL development stages.
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Shift Left using AutoCheck Formal Verification
Resource (Slides (.PDF)) - May 20, 2025 by Mitchell Poplingher
In this session we will demonstrate automated applications with formal verification under-the-hood can truly enable a “shift left”.
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Addressing the Emerging Challenges in DFT Verification with QDX
Conference - May 20, 2025 by Jake Wiltgen
The rise of AI accelerators, coupled with multi-die integration and heterogeneous architectures, has driven unprecedented complexity in semiconductor design, making advanced DFT implementations essential to meeting increasingly rigorous quality requirements. In this session we will showcase exciting optimization results obtained by QDX flow in real customer designs.
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Addressing the Emerging Challenges in DFT Verification with QDX
Resource (Slides (.PDF)) - May 20, 2025 by Jake Wiltgen
In this session we will showcase exciting optimization results obtained by QDX flow in real customer designs.
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Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture
Resource (Paper (.PDF)) - May 20, 2025 by Ann Keffer
This paper demonstrates an integrated, cohesive safety workflow to address the challenges of achieving ISO 26262 compliance and ensure efficient tracking and management of safety-related information, from initial safety analysis to final validation and compliance.
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Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture
Paper - May 20, 2025 by Ann Keffer
The ISO 26262 standard underscores the importance of achieving specific random hardware failure rate targets for each automotive safety integrity level and provides a comprehensive framework for assessing, mitigating, and validating random hardware failures. This paper demonstrates an integrated, cohesive safety workflow to address ISO 26262 compliance and ensure efficient tracking and management of safety-related information, from initial safety analysis to final validation and compliance.
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Breaking the Formal Verification Bottleneck: Faster, Comprehensive Testing for Parameterized Modules
Conference - May 13, 2025 by Ariel Ansbacher - Veriest
In the session, we will delve into the P2S methodology, showcase its implementation using our custom compiler, and present a detailed comparison of the P2S approach versus traditional techniques across various design blocks using Questa Formal.
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Breaking the Formal Verification Bottleneck: Faster, Comprehensive Testing for Parameterized Modules
Resource (Slides (.PDF)) - May 13, 2025 by Ariel Ansbacher - Veriest
This session addresses the challenges of verifying parameterized SoCs designs using Formal Verification. Traditional methods, which involve testing each parameter configuration separately, result in increased test counts, longer runtimes, and incomplete coverage.
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Accelerating Coverage Closure using Questa Verification IQ Coverage Analyzer & CoverCheck
Resource (Slides (.PDF)) - May 13, 2025 by Elvin Serrao - Arm
In most of the verification flows today, coverage is one of the metrics to determine if verification is completed. The code and functional coverage are two broad categories of coverage which are monitored and tracked for verification sign-off.
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Accelerating Coverage Closure using Questa Verification IQ Coverage Analyzer & CoverCheck
Conference - May 13, 2025 by Elvin Serrao - Arm
This session demonstrates a methodology of how Questa Unreachability (UNR) flow is integrated with Verification IQ (VIQ) tool for accelerating coverage closure. In most of the verification flows today, coverage is one of the metrics to determine if verification is completed. The code and functional coverage are two broad categories of coverage which are monitored and tracked for verification sign-off.
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Verification of a NAND flash memory controller using UVMF and CDC
Resource (Slides (.PDF)) - May 13, 2025 by Jonas Källén - Frontgrade Gaisler
This session will relate to introducing UVM framework and Questa CDC checker for IP development. We'll discuss improvements made through these methods, as well as lessons learned. We'll then cover both the UVM setup, including how the data and control flows were tested.
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Verification of a NAND flash memory controller using UVMF and CDC
Conference - May 13, 2025 by Jonas Källén - Frontgrade Gaisler
This session will relate to introducing UVM framework and Questa CDC checker for IP development. We'll discuss improvements made through these methods, as well as lessons learned. We'll then cover both the UVM setup, including how the data and control flows were tested.
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Covering Fast to Slow Frequency Crossing Analysis using Questa CDC
Resource (Slides (.PDF)) - May 13, 2025 by Amaury Breme - NXP
In the System on Chip (SoC) digital design flow, the occurrence of fast to slow crossings is a prevalent phenomenon, characterized by a source flop being clocked at a higher frequency than the destination. Such crossings pose a significant risk of inducing tangible silicon-related challenges.
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Covering Fast to Slow Frequency Crossing Analysis using Questa CDC
Conference - May 13, 2025 by Amaury Breme - NXP
This session presents a novel approach to address this gap by introducing a robust solution for conducting thorough fast to slow crossing analysis through Clock Domain Crossing (CDC) checks. By leveraging this methodology, the study aims to enhance the Quality of Results (QoR) in digital design processes, ensuring the mitigation of risks associated with fast to slow crossings.
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Functional Verification of an L2 Cache Coherent System using Avery CHI VIP
Conference - May 13, 2025 by Gregory Faux - Kalray
In this session, you will learn more about our cache coherency background and challenges, L2 verification strategy, environment configuration, stimuli generation, metrics collection and debug.
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Functional Verification of an L2 Cache Coherent System using Avery CHI VIP
Resource (Slides (.PDF)) - May 13, 2025 by Gregory Faux - Kalray
In this session, you will learn more about our cache coherency background and challenges, L2 verification strategy, environment configuration, stimuli generation, metrics collection and debug.
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Better Stimulus Generation Through AI
Paper - May 13, 2025 by Tom Fitzpatrick
As semiconductor designs grow increasingly complex, verification teams face mounting pressure to ensure design correctness while meeting aggressive time-to-market demands. While PSS offers powerful capabilities for creating reusable verification assets, there are perceived adoption limitations. This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.
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Better Stimulus Generation Through AI
Resource (Paper (.PDF)) - May 13, 2025 by Tom Fitzpatrick
This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.
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Reach the Finish Line Faster: How Questa One Speeds Total Simulation Turnaround Time
Resource (Paper (.PDF)) - May 13, 2025 by Sunil Sahoo
Questa™ One Sim’s SmartCompile emerges as a strategic solution for reducing the overall verification timeline, offering a comprehensive set of tools that substantially reduce the turnaround time from initial compilation to final simulation.
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Reach the Finish Line Faster: How Questa One Speeds Total Simulation Turnaround Time
Paper - May 13, 2025 by Sunil Sahoo
Questa™ One Sim’s SmartCompile emerges as a strategic solution for reducing the overall verification timeline, offering a comprehensive set of tools that substantially reduce the turnaround time from initial compilation to final simulation. By integrating advanced capabilities with optimized coding style improvements, SmartCompile delivers a more efficient design flow that directly addresses the challenges of modern digital design development.
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Raising the Bar in Mission-Critical Verification: Aerospace and Defense Trends Analysis of FPGA Design Practices
Resource (Paper (.PDF)) - May 13, 2025 by Harry Foster
The insights presented in this report serve as a valuable benchmark for A&D organizations aiming to evaluate and enhance their verification maturity, technology adoption, and engineering resource alignment in response to evolving challenges.
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Raising the Bar in Mission-Critical Verification: Aerospace and Defense Trends Analysis of FPGA Design Practices
Paper - May 13, 2025 by Harry Foster
The 2024 Siemens EDA and Wilson Research Group Functional Verification Study provides an in-depth analysis of current trends in FPGA design and verification, with a particular focus on the aerospace and defense (A&D) sector. The study highlights the increasing complexity of FPGA designs driven by factors such as embedded processors, asynchronous clock domains, and stringent security and safety-critical requirements.
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Turning Vision into Reality: How Questa One Fulfills the Promise of Smart Verification
Resource (Paper (.PDF)) - May 13, 2025 by Harry Foster
In this white paper, you will learn how Questa One delivers a next-generation solution engineered to turn verification from a bottleneck into a competitive advantage.
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Turning Vision into Reality: How Questa One Fulfills the Promise of Smart Verification
Paper - May 13, 2025 by Harry Foster
Verification is no longer just a step in the design flow—it’s rapidly becoming the biggest barrier to innovation. In response, Siemens offers a transformative shift toward verification that is connected, data-driven, and scalable. Questa One delivers a next-generation solution engineered to turn verification from a bottleneck into a competitive advantage.