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New School Coverage Closure
Webinar - May 29, 2015 by Mark Eslinger
In this session, you will learn a new school formal verification method which automates the job of focusing coverage closure efforts.
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Introduction to Questa X-Check
Webinar - Dec 20, 2014 by Doug Smith
In this session, you will learn how Questa X-Check finds sources of X in your design and identifies issues where X is propagated and corrupts properly initialized registers.
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Introduction to Questa CDC
Webinar - Nov 12, 2014 by Doug Smith
In this session, you will learn how the Questa Clock-Domain Crossing (CDC) solution focuses on the interaction between these clock-domains.
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Introduction to Questa CoverCheck
Webinar - Oct 16, 2014 by Doug Smith
In this session, you will learn how Questa CoverCheck automates and accelerates the process of code coverage closure.
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Establishing a Company Wide Verification Reuse Library
Webinar - Oct 15, 2014 by Bob Oden
In this session, you will learn how to outline key characteristics of a reuse verification library and will outline a proven reuse methodology.
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Navigating the Perfect Storm: New School Verification Solutions
Webinar - Oct 15, 2014 by Tom Fitzpatrick
This session introduces today’s trends and challenges in SoC design and verification and outlines a path for navigating this “perfect storm."
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Verification and Debug: Old School Meets New School
Webinar - Oct 15, 2014 by Rich Edelman
You will learn how to use the best of old and new school debug techniques to find problems faster and to better answer “am I done yet”.
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UVM Sequences in Depth
Webinar - Aug 12, 2014 by Tom Fitzpatrick
In this session, we will walk through the mechanics of setting up and executing Slave Sequences in a responder. We will also walk through modeling an interrupt sequence and show how to have interrupt sequences running in conjunction with other stimulus sequences.
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UVM: What's New, What's Next and Why You Care
Webinar - Jun 25, 2014 by Tom Fitzpatrick
This session will teach you everything you need to know about the future of UVM. We'll briefly cover the new features included in UVM1.2 and how to minimize their impact, and we'll identify the key subset of UVM features that will make your environment truly reusable from block to system-level verification while providing the ideal platform for integrating new solutions and standards.
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UVM 1.2 is Coming: So Be Prepared
Webinar - May 15, 2014 by Tom Fitzpatrick
In this session, you will learn everything you need to know about the future of UVM including new features, performance, backward-compatibility concerns and more.
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Questa Verification IP: More Than Just a BFM
Webinar - Feb 12, 2014 by Tom Fitzpatrick
Today’s advanced UVM environments require more than a standard BFM to support environment reuse, randomized stimulus, generation of traffic scenarios, coverage collection, etc.
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Raising Productivity Using Abstract UVM Stimulus and Intelligent Automation
Webinar - Oct 18, 2013 by Tom Fitzpatrick
In this session, you will be introduced to the abstract stimulus specification that provides more effective UVM tests that can be reused throughout your SoC flow.
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Automating the Creation of Your UVM Register Model
Webinar - Aug 15, 2013 by Tom Fitzpatrick
In this session, you will be introduced to the UVM Register Assistant that will show how to generate correct-by-construction register models and tests from a register specification.
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Effectively Modeling and Analyzing Coverage
Webinar - Nov 15, 2012 by Tom Fitzpatrick
In this session, we will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret.
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More About UVM Registers
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn how to implement registers and score-boarding at the register layer.
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Protocol Layering in UVM
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.
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Introduction to UVM Registers
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will be introduced to the Register Layer and how to get started writing tests and sequences and checking results at the register layer.
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C-Based Stimulus for UVM
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn more about a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents.
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UVM Debug
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this Verification Cookbook session, you will learn how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.
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UVM Scoreboarding and Results Prediction
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn how to outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.
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OVM to UVM Migration
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session you will be introduced to a step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.
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Customization in UVM
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT and how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.
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Transforming Verification and Verification Management
Webinar - Apr 08, 2011 by Tom Fitzpatrick
This session leads-off where all successful verification projects begin: verification planning and management. This includes verification plan creation, real-time tracking of progress against the plan, and analyzing results and trends throughout the project.
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Power Aware Verification and UPF Tricks
Webinar - Apr 08, 2011 by Tom Fitzpatrick
In this session, you will learn how to apply low power design techniques with UPF to augment an existing flow for RTL and netlist.
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Industry Perspective & Opportunities in ABV
Webinar - Jan 15, 2010 by Harry Foster
In this session, you will learn about Industry Perspective and Opportunities in ABV.