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Webinar (209)
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209 Results

  • Should I Kill My Formal Run? Part 2: Avoid Trouble and Set Yourself Up For Success

    Webinar - Sep 01, 2020 by Jin Hou

    In this session we assume you are about to kick off a formal analysis, and want to make sure you will avoid the most obvious pitfalls in setting up your formal testbench, the DUT, and the runner scripting.

  • Stimulating Simulating: UVM Transactions

    Webinar - Aug 26, 2020 by Chris Spear

    In this session, you will learn how to create classes for UVM transactions, also known as sequence items. You will also be shown how to add new functionality to a transaction, by extending the class and much more.

  • Verilog Basics for SystemVerilog Constrained Random Verification

    Webinar - Aug 18, 2020 by Dave Rich

    In this session we will review two of the most common issues when constraint solver results do not match your intent: 1) not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra, and 2) not understanding the affect probability has on choosing solution values.

  • When Are You Done Running CDC?

    Webinar - Jul 16, 2020 by Chris Giles

    In this session you will learn whether or not you might still have asynchronous clock or reset issues lurking in your design, despite having identified the crossings, ensured synchronizers are present, and reviewed your code – or even already run CDC analysis, ensuring that all CDCs are solid.

  • Get Your Bits Together: SystemVerilog Structures and Packages

    Webinar - Jul 14, 2020 by Chris Spear

    In this session, you will learn best practices for structures and packages in the SystemVerilog language and how you can combine related definitions for data types, parameters, classes, and more into a package that is easily shared and reused.

  • Simplifying Questa Usage and Deployment with Qrun

    Webinar - Jul 09, 2020 by Tom Kiley

    In this session, you will learn how to reduce the complexity of compiling, optimizing, elaborating, and simulating your design. Qrun encapsulates the details of the QuestaSim tool invocation. Users commonly write scripts or makefiles to encapsulate these steps.

  • Introduction to Visualizer for the VHDL Users

    Webinar - Jun 30, 2020 by Rich Edelman

    This session will introduce the Visualizer Debug Environment for VHDL and UVM.

  • Introduction to Visualizer for the Verilog Users

    Webinar - Jun 16, 2020 by Rich Edelman

    This session will introduce the Visualizer Debug Environment for Verilog and UVM.

  • ISO 26262 Functional Safety for Autonomous Vehicles

    Webinar - Jun 11, 2020 by Jake Wiltgen

    When verifying safety critical systems, the stakes are raised in ensuring that bugs/defects are not introduced into production with many standards striving for zero defective parts per million. The powerful combination of Siemens EDA Functional Verification and Functional Safety products together with Siemens’ Lifecycle Management tools provide built-in guidance and automation helping you navigate the difficult waters of safety compliance.

  • Confronting Inevitability: Finding Clock and Reset Issues Before They Find You

    Webinar - Jun 11, 2020 by Chris Giles

    In this session, you will learn the full scope of synchronization issues and how Questa’s clock- and reset-domain crossing solution will help you avoid costly design flaws and accelerate your time to market.

  • Taking SystemVerilog Arrays to the Next Dimension

    Webinar - Jun 05, 2020 by Chris Spear

    In this session, you will learn the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. As a result, your testbench code will be easier to understand and reuse, run faster, and consume less memory.

  • Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal

    Webinar - Jun 04, 2020 by Joe Hupcey

    In this session, you will learn how formal apps can help you address high-value verification challenges; finding deep bugs in complex logic, accelerating code coverage closure, uncovering register policy corner cases, validating low power clock gating, late ECOs or bug fixes, or fault/SEU mitigation logic and more.

  • Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal

    Webinar - Jun 04, 2020 by Mark Eslinger

    In this session, you will learn how formal analysis works, how you can create an effective "formal testbench" with very basic, easy-to-write properties, plus an introduction to popular formal verification methodologies: bug hunting, completely proving the correctness of critical DUT functions, and proving the absence of deadlock.

  • Deadlock Verification For Dummies - The Easy Way Using SVA and Formal

    Webinar - Jun 02, 2020 by Mark Eslinger

    In this session we will show how combining the above concepts using normal SVA liveness properties allows for RTL engineers to achieve the benefit of formal deadlock analysis without the iterative component or learning a non-standard assertion language. Deadlock verification for dummies!

  • Better UVM Debug with Visualizer

    Webinar - Jun 02, 2020 by Rich Edelman

    In this session you will learn UVM Debug tips and tricks in both Post simulation and Live simulation.

  • Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP

    Webinar - May 28, 2020 by Munish Goyal

    In this session, you will learn how the Questa Verification IP library gives you everything you need to verify standard protocols in your UVM environment. With the new Configurator GUI, it's now even easier to take advantage of these powerful verification components to maximize the effectiveness of your UVM verification.

  • Market-Driven Trends in Hardware Emulation

    Webinar - May 21, 2020 by Vijay Chobisa

    In this session you will learn how AI/ML, 5G, networking and ADAS designs are affecting verification and validation and how Veloce Strato & VirtuaLAB address these verification challenges.

  • Context-Aware Debug for Complex Heterogeneous Environments

    Webinar - May 21, 2020 by Rich Edelman

    In this session, you will learn how you can debug using high level abstractions like classes, transactions, assertions, coverage, biometric search, automated temporal causality trace and how you can utilize Visualizer to tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …).

  • Productivity in the Questa Simulation Flow

    Webinar - May 15, 2020 by Gordon Allan

    In this session, you will learn every step of the Questa Simulation-based verification flow has been optimized and accelerated, from regression management, to incremental compilation and elaboration, to debug and coverage.

  • Optimizing Time to Bug

    Webinar - May 15, 2020 by Tom Fitzpatrick

    In this session, we'll be highlighting the issues that have cropped up in recent years, including the explosion in the amount of data that must now be verified and managed and the safety and security of the data and systems they control.

  • UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know

    Webinar - Apr 10, 2020 by Chris Spear

    In this session, you will learn how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs.

  • Mind the Gap(s): Closing and Creating Gaps Between Design and Verification

    Webinar - Mar 31, 2020 by Chris Giles

    This session will examine several gaps in development processes that can result in verification escapes, and suggest solutions that can prevent bugs from finding their way into customer deployments.

  • FPGA Verification Maturity: A Quantitative Analysis

    Webinar - Mar 26, 2020 by Harry Foster

    While multiple studies on IC/ASIC functional verification trends have been published, there have been no studies specifically focused on FPGA verification trends. To address this dearth of information, Harry presents the results from a recent large industry study on functional verification.

  • Why Reset Domain Crossing Verification is an Emerging Requirement

    Webinar - Oct 01, 2019 by Kurt Takara

    In this session, you will learn what RDC covers that CDC does not and the appropriate time in the development cycle to deploy RDC.

  • Clock-Domain Crossing Analyses and Verification

    Webinar - Jul 10, 2019 by Kurt Takara

    This session explains the importance of a complete CDC methodology to produce error-free silicon.