BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

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Wednesday, Feb 04th-9:30 AM PST

Avery Verification IP for AI/ML/HPC | Santa Clara, CA

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Thursday, Feb 05th-8:00 AM PST

Close Coverage Faster with Questa One Sim's Unreachability Analysis

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Wednesday, Feb 11th-12:00 PM PST

Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

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Wednesday, Feb 18th-10:00 AM PST

Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

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Thursday, Feb 19th-7:30 AM PST

Discussing the AI/ML paradigm shift across the industry.

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Tuesday, Feb 24th-9:30 AM PST

Discussing the latest advancements in RTL simulation.

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Webinar (216)
Intermediate (115)
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Advanced (5)

216 Results

  • I'm Excited About Formal...My Journey From Skeptic To Believer

    Webinar - Feb 26, 2021 by Neil Johnson

    In this session, you will learn the about unlikely journey into formal for a verification engineer who’s spent an entire career using simulation.

  • A Methodology for Comprehensive CDC Analysis

    Webinar - Feb 26, 2021 by Atul Sharma

    In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.

  • The ABC of Formal Verification

    Webinar - Feb 11, 2021 by Dr. Ashish Darbari

    This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.

  • Embedded Software Debug Using Codelink and Visualizer

    Webinar - Dec 08, 2020 by Tomasz Piekarz

    In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.

  • Visualizer Coverage: Debug and Visualize All Your Coverage

    Webinar - Nov 19, 2020 by Athira Panicker

    In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.

  • Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer

    Webinar - Oct 27, 2020 by Jason Polychronopoulos

    This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.

  • Reducing Area & Power Consumption with Formal-based ‘X’ Verification

    Webinar - Oct 15, 2020 by Ping Yeung

    In this session we will share a comprehensive static and formal-based methodology employing this app that enables design teams to root cause ‘X’ issues early in the RTL design process.

  • Stimulating Simulating 2: UVM Sequences

    Webinar - Oct 08, 2020 by Chris Spear

    In this session, you will learn more about UVM Sequences; creating classes, transactions flow and virtual sequences. In addition, Chris will share best practices with UVM sequence classes.

  • Should I Kill My Formal Run? Part 2: Avoid Trouble and Set Yourself Up For Success

    Webinar - Sep 01, 2020 by Jin Hou

    In this session we assume you are about to kick off a formal analysis, and want to make sure you will avoid the most obvious pitfalls in setting up your formal testbench, the DUT, and the runner scripting.

  • Stimulating Simulating: UVM Transactions

    Webinar - Aug 26, 2020 by Chris Spear

    In this session, you will learn how to create classes for UVM transactions, also known as sequence items. You will also be shown how to add new functionality to a transaction, by extending the class and much more.

  • Verilog Basics for SystemVerilog Constrained Random Verification

    Webinar - Aug 18, 2020 by Dave Rich

    In this session we will review two of the most common issues when constraint solver results do not match your intent: 1) not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra, and 2) not understanding the affect probability has on choosing solution values.

  • When Are You Done Running CDC?

    Webinar - Jul 16, 2020 by Chris Giles

    In this session you will learn whether or not you might still have asynchronous clock or reset issues lurking in your design, despite having identified the crossings, ensured synchronizers are present, and reviewed your code – or even already run CDC analysis, ensuring that all CDCs are solid.

  • Get Your Bits Together: SystemVerilog Structures and Packages

    Webinar - Jul 14, 2020 by Chris Spear

    In this session, you will learn best practices for structures and packages in the SystemVerilog language and how you can combine related definitions for data types, parameters, classes, and more into a package that is easily shared and reused.

  • Simplifying Questa Usage and Deployment with Qrun

    Webinar - Jul 09, 2020 by Tom Kiley

    In this session, you will learn how to reduce the complexity of compiling, optimizing, elaborating, and simulating your design. Qrun encapsulates the details of the QuestaSim tool invocation. Users commonly write scripts or makefiles to encapsulate these steps.

  • Introduction to Visualizer for the VHDL Users

    Webinar - Jun 30, 2020 by Rich Edelman

    This session will introduce the Visualizer Debug Environment for VHDL and UVM.

  • Introduction to Visualizer for the Verilog Users

    Webinar - Jun 16, 2020 by Rich Edelman

    This session will introduce the Visualizer Debug Environment for Verilog and UVM.

  • ISO 26262 Functional Safety for Autonomous Vehicles

    Webinar - Jun 11, 2020 by Jake Wiltgen

    When verifying safety critical systems, the stakes are raised in ensuring that bugs/defects are not introduced into production with many standards striving for zero defective parts per million. The powerful combination of Siemens EDA Functional Verification and Functional Safety products together with Siemens’ Lifecycle Management tools provide built-in guidance and automation helping you navigate the difficult waters of safety compliance.

  • Confronting Inevitability: Finding Clock and Reset Issues Before They Find You

    Webinar - Jun 11, 2020 by Chris Giles

    In this session, you will learn the full scope of synchronization issues and how Questa’s clock- and reset-domain crossing solution will help you avoid costly design flaws and accelerate your time to market.

  • Taking SystemVerilog Arrays to the Next Dimension

    Webinar - Jun 05, 2020 by Chris Spear

    In this session, you will learn the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. As a result, your testbench code will be easier to understand and reuse, run faster, and consume less memory.

  • Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal

    Webinar - Jun 04, 2020 by Joe Hupcey

    In this session, you will learn how formal apps can help you address high-value verification challenges; finding deep bugs in complex logic, accelerating code coverage closure, uncovering register policy corner cases, validating low power clock gating, late ECOs or bug fixes, or fault/SEU mitigation logic and more.

  • Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal

    Webinar - Jun 04, 2020 by Mark Eslinger

    In this session, you will learn how formal analysis works, how you can create an effective "formal testbench" with very basic, easy-to-write properties, plus an introduction to popular formal verification methodologies: bug hunting, completely proving the correctness of critical DUT functions, and proving the absence of deadlock.

  • Deadlock Verification For Dummies - The Easy Way Using SVA and Formal

    Webinar - Jun 02, 2020 by Mark Eslinger

    In this session we will show how combining the above concepts using normal SVA liveness properties allows for RTL engineers to achieve the benefit of formal deadlock analysis without the iterative component or learning a non-standard assertion language. Deadlock verification for dummies!

  • Better UVM Debug with Visualizer

    Webinar - Jun 02, 2020 by Rich Edelman

    In this session you will learn UVM Debug tips and tricks in both Post simulation and Live simulation.

  • Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP

    Webinar - May 28, 2020 by Munish Goyal

    In this session, you will learn how the Questa Verification IP library gives you everything you need to verify standard protocols in your UVM environment. With the new Configurator GUI, it's now even easier to take advantage of these powerful verification components to maximize the effectiveness of your UVM verification.

  • Market-Driven Trends in Hardware Emulation

    Webinar - May 21, 2020 by Vijay Chobisa

    In this session you will learn how AI/ML, 5G, networking and ADAS designs are affecting verification and validation and how Veloce Strato & VirtuaLAB address these verification challenges.