FPGA Webinar

Wednesday, Jul 22nd-8:00 AM PDT

Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

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BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

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DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

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Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

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Webinar (225)
Intermediate (121)
Beginner (99)
Advanced (5)

225 Results

  • CDC Verification: Beyond Structural Analysis

    Webinar - Jul 29, 2021 by Mark Handover

    In this session, we will cover the overall CDC methodology and cover CDC protocols and reconvergence in more details and show what could happen if these steps are skipped.

  • Mitigating the Effects of Random Hardware Faults

    Webinar - Jul 29, 2021 by Dirk Hansen - Siemens EDA

    Random faults cannot be prevented so the goal there is to sufficiently tolerate them. With random faults you are really just trying to make sure that the product will fail safely when inevitably one of these random hardware faults occurs. In this session we will outline approaches on how to tackle systematic as well as random faults.

  • AMS Functional Verification for Safety-Critical Automotive Applications

    Webinar - Jul 29, 2021 by Sumit Vishwakarma

    In this session, you will learn how Siemens EDA Symphony platform addresses today's nanometer mixed signal verification challenges for safety-critical automotive applications.

  • A Path to Develop Safe ICs - Part 2

    Webinar - Jul 29, 2021 by Stephanie Dournelle, Paul Williams - Siemens EDA

    In this session you will learn that Siemens EDA has developed a platform that allows early collaboration between OEMs and their suppliers. It provides a clear definition of requirements and allows hardware and software functionality to be tested in a virtual environment long before silicon is available.

  • A Path to Develop Safe ICs - Part 1

    Webinar - Jul 29, 2021 by Stephanie Dournelle - Siemens EDA

    In this session, you will learn that Siemens EDA helps customers adapt to the required development flows, develop safety collateral for their designs, and mitigate the risk of product failure in safety critical applications.

  • Extending the Role of Test and In-System Test to Meet Automotive Safety and Security Requirements

    Webinar - Jul 29, 2021 by Lee Harrison

    In this session, we will show how Design For Test is expanding from its traditional role into one that includes the management of the entire silicon lifecycle, to become Silicon Lifecycle Solutions. Ensuring that ICs work safely as expected and are secure throughout their operational life.

  • Hardware-Accelerated & Software-Driven Verification

    Webinar - Jul 29, 2021 by Ajay Sharma

    In this session we will talk about ease of adopting Emulation and various ways of using the powerful Apps that bring in software to improve accuracy of verification process.

  • Automotive SOTIF Compliance for Arm with PAVE360

    Webinar - Jul 29, 2021 by Joseph Dailey

    In this session, we will explain Safety Of The Intended Function (SOTIF) and demonstrate techniques to prove systems.

  • Are Random Hardware Faults Common?

    Webinar - Jul 29, 2021 by Dirk Hansen - Siemens EDA

    In this session, you will be given an introduction of solutions to analysis failure modes resulting from random hardware faults. These can guide the user to unsafe areas of the design where safety mechanisms need to be inserted.

  • Traceability for Automotive Standards Compliance

    Webinar - Jul 29, 2021 by Darron May

    In this session, you will learn how the combination of Siemens Polarion ALM Requirements Management and Questa Verification Management solve the lifecycle management and traceability requirements for Automotive projects.

  • The Future of Automotive and its Impact on Safety

    Webinar - Jul 29, 2021 by Ann Keffer

    This session will provide a perspective on the impact to companies developing automotive ICs and serves as the introduction to the multi-part automotive safety webinar series covering many aspects of an automotive safety lifecycle.

  • Part II: Verification of PCIe® IP

    Webinar - Jul 15, 2021 by Stephane Hauradou

    In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.

  • Equivalence Checking for FPGA

    Webinar - Jul 06, 2021 by Martin Rowe

    In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.

  • Leveraging Advancements in UPF 3.1 for Effective Design and Verification

    Webinar - Jun 23, 2021 by Gabriel Chidolue

    In this session, you will learn about some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.

  • Part I: Introduction to PCIe® Gen 6

    Webinar - Jun 08, 2021 by Gordon Allan

    In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe® 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

  • Optimizing a Fault Campaign for Complex Mixed-Signal Devices

    Webinar - May 04, 2021 by Jake Wiltgen

    In this session, you will learn details how to effectively set up and execute an ISO 26262 fault campaign for mixed signal designs and establishing an efficient fault injection workflow for analog and digital portions of the design.

  • Low Power Considerations for Verification

    Webinar - Apr 29, 2021 by Rick Koster

    Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.

  • A Methodology for Comprehensive CDC+RDC Analysis

    Webinar - Apr 20, 2021 by Kurt Takara

    In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability.

  • Easy Test Writing with a Proxy-driven Testbench

    Webinar - Apr 06, 2021 by Ray Salemi

    In this session we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.

  • Functional Debug: Verification and Beyond

    Webinar - Mar 31, 2021 by Hanan Moller

    In this session, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture.

  • Making Your DPI-C Interface a Fast River of Data

    Webinar - Mar 31, 2021 by Rich Edelman

    This session will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.

  • Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

    Webinar - Mar 31, 2021 by Progyna Khondkar

    This session distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.

  • “Bounded Proof” Sign-Off with Formal Coverage

    Webinar - Mar 31, 2021 by Joe Hupcey

    In this session, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.

  • I Didn’t Know Visualizer Could Do That

    Webinar - Mar 30, 2021 by Rich Edelman

    In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

  • Preventing Glitch Nightmares on CDC Paths

    Webinar - Mar 26, 2021 by Ping Yeung

    As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths.