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The Future of Automotive and its Impact on Safety

Webinar - Jul 29, 2021 by Ann Keffer

This session will provide a perspective on the impact to companies developing automotive ICs and serves as the introduction to the multi-part automotive safety webinar series covering many aspects of an automotive safety lifecycle.
Part II: Verification of PCIe® IP

Webinar - Jul 15, 2021 by Stephane Hauradou

In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.
Equivalence Checking for FPGA

Webinar - Jul 06, 2021 by Martin Rowe

In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.
Leveraging Advancements in UPF 3.1 for Effective Design and Verification

Webinar - Jun 23, 2021 by Gabriel Chidolue

In this session, you will learn about some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.
Part I: Introduction to PCIe® Gen 6

Webinar - Jun 08, 2021 by Gordon Allan

In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe® 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.
Optimizing a Fault Campaign for Complex Mixed-Signal Devices

Webinar - May 04, 2021 by Jake Wiltgen

In this session, you will learn details how to effectively set up and execute an ISO 26262 fault campaign for mixed signal designs and establishing an efficient fault injection workflow for analog and digital portions of the design.
Low Power Considerations for Verification

Webinar - Apr 29, 2021 by Rick Koster

Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.
A Methodology for Comprehensive CDC+RDC Analysis

Webinar - Apr 20, 2021 by Kurt Takara

In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability.
Easy Test Writing with a Proxy-driven Testbench

Webinar - Apr 06, 2021 by Ray Salemi

In this session we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.
Functional Debug: Verification and Beyond

Webinar - Mar 31, 2021 by Hanan Moller

In this session, we will discuss the features of functional debug solutions and the benefits they bring throughout the SoC development process.
Making Your DPI-C Interface a Fast River of Data

Webinar - Mar 31, 2021 by Rich Edelman

This session will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

Webinar - Mar 31, 2021 by Progyna Khondkar

This session distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.
Functional Debug: Verification and Beyond

Webinar - Mar 31, 2021 by Hanan Moller

In this session, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture.
“Bounded Proof” Sign-Off with Formal Coverage

Webinar - Mar 31, 2021 by Joe Hupcey

In this session, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.
I Didn’t Know Visualizer Could Do That

Webinar - Mar 30, 2021 by Rich Edelman

In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.
Preventing Glitch Nightmares on CDC Paths

Webinar - Mar 26, 2021 by Ping Yeung

As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths.
The Life of a SystemVerilog Variable

Webinar - Mar 26, 2021 by Dave Rich

This session presents a background on the different categories of variable lifetimes, what their intended use models are, and how improper usage can be corrected.
ModelSim to Questa - Productivity Features

Webinar - Mar 25, 2021 by Jonathan Craft

In this session, you will gain an understanding of the differences between the ModelSim and Questa simulators and will be introduced to the advanced verification techniques and methodology necessary for design and verification of high-end FPGA and ASIC.
Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Webinar - Mar 25, 2021 by Ray Salemi

This session introduces `pyuvm`, a Python implementation of IEEE Spec 1800.2. It discusses the Python tricks used to implement UVM features such as the factory, FIFOs, and config_db.
Spiral Refinement Methodology for Silicon Bug Hunt

Webinar - Mar 24, 2021 by Mark Eslinger

In this session, we capture the refinement process into a step-by-step methodology, formulate it graphically so that it is easy to understand and replicate.
Advance your Designs with Advances in CDC and RDC

Webinar - Mar 23, 2021 by Kurt Takara

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC.
Automatic Formal Verification - Questa Static and Formal Apps

Webinar - Mar 21, 2021 by Walter Gude

In this session, you will gain an understanding of the automatic formal applications that can be used to solve current design and verification challenges.
How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

Webinar - Mar 18, 2021 by Joon Hong

In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.
Practical Flows for Continuous Integration: Making the Most of Your EDA Tools

Webinar - Mar 16, 2021 by Neil Johnson

In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.
Trends in Functional Verification

Webinar - Mar 02, 2021 by Harry Foster

Adopting proven solutions to achieve functional correctness has become critical. In this talk Harry will explore today’s functional verification landscape and present the latest industry trends.