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Webinar (210)
Intermediate (115)
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210 Results

  • The Three Pillars of Intent-Focused Insight

    Webinar - Jun 08, 2022 by Harry Foster

    This session reviews the impact of today’s verification crisis, identifies the fundamental problem contributing to this crisis, and then prescribes a solution.

  • Siemens and the US Government - Mitigating Microelectronics Development Challenges

    Webinar - May 10, 2022 by Rich Powlowsky

    In this session, you will learn how Siemens is a full solution provider to the fabless design community, including SoCs and Heterogeneous Integration from concept through GDSII sign off, through to the manufactured wafer and product life cycle.

  • Bringing Model-based Systems Engineering to IC and FPGA Design

    Webinar - May 10, 2022 by Ray Salemi

    In this session, you will learn how international competition has forced the change, how model-based design will change the way the Defense Industrial Base works with the DoD, and what all this means for IC verification.

  • From Model to Implementation with High-Level Synthesis

    Webinar - May 10, 2022 by Russell Klein

    In this session, you will learn how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.

  • Accelerate Learning Curves and Achieve Program Goals Efficiently

    Webinar - May 10, 2022 by Chris Giles

    In this session, you will learn how Questa Design Solutions accelerates development learning and improves and instruments development efficiency by providing design quality insight early, then monitoring throughout development.

  • Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach

    Webinar - May 10, 2022 by Bob Oden

    In this session, you'll learn how the UVM Framework and Questa Verification IP enables testbench creation in a day so the team can focus on creating tests and closing coverage.

  • How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification

    Webinar - May 10, 2022 by Joe Hupcey

    In this session, you will learn about the unique capabilities in Siemens EDA's formal solutions , then share a case study on how automated formal "unreachability" analysis can accelerate overall verification coverage closure via integration with QuestaSim.

  • Accelerate Development Using Advanced Debugging Approaches

    Webinar - May 10, 2022 by Rich Edelman

    In this session, you will learn how Visualizer Debug Environment provides a high-performance, high-capacity, tightly integrated debug environment for Simulation and Emulation.

  • Collaborative Verification Management & Coverage Analysis

    Webinar - May 10, 2022 by Darron May

    In this session, you will learn of the applications which comprise VIQ, which help manage all verification tasks including test plan creation, coverage analysis, regression management, and metric trending.

  • Securing the Electronics Development Chain with IC Integrity Solutions

    Webinar - May 10, 2022 by John Hallman

    In this session we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking for this very complex IC integrity challenge.

  • System Level SoC Verification and Validation Using Emulation and Prototype Platforms

    Webinar - May 10, 2022 by Vijay Chobisa

    This session covers the Veloce Strato+ emulation platform, delivering fast execution speed, full debug visibility, flexible use models, and ease-of-use in models that span the entire range of needs throughout the life of the chip/SoC development process.

  • Trust but Verify Your IP with Solido Crosscheck

    Webinar - May 10, 2022 by Felipe Schneider

    This session will show Solido Crosscheck as the one-stop-shop solution for IP validation and QA accountability among IP designers and IP integrators.

  • Formal 101 - Fast, Scalable Formal Verification Made Easy

    Webinar - Mar 17, 2022 by Joe Hupcey

    In this session, we will give an overview of how to apply basic abstractions, how to set up & optimize constraints, and where and how to leverage Data Independence & Non-Determinism.

  • Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

    Webinar - Mar 10, 2022 by Buu Huynh

    This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost.

  • Equivalence Checking for FPGA

    Webinar - Feb 25, 2022 by Martin Rowe

    In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.

  • Achieving High Defect Coverage for Safety Critical and High Reliability Designs

    Webinar - Feb 22, 2022 by Lee Harrison

    In this session you will gain an understanding of how Siemens EDA provides practices, methodologies and integrated tool flows that provides a path to reaching the required manufacturing test quality needed for designs targeted at critically safe and high reliability markets.

  • ‘The Dog Ate my RTL’ Doesn’t Work Anymore

    Webinar - Feb 15, 2022 by Joe Hupcey

    In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

  • Introduction to Questa Lint and CDC for Designers

    Webinar - Jan 25, 2022 by Mathew Yee

    In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.

  • Validation of Complex Safety Architectures

    Webinar - Nov 18, 2021 by Vedant Garg

    This session explains the methodology and flow of how to perform an accurate safety analysis, followed by fault simulation on the SoC or IP with a combination of hardware and software safety mechanisms.

  • Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies

    Webinar - Nov 02, 2021 by Kurt Takara

    In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised.

  • CDC Philosophy: The Existential Questions of Constraints, Waivers, and Truth

    Webinar - Oct 12, 2021 by Kurt Takara

    In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly.

  • Improving Initial RTL Quality

    Webinar - Sep 15, 2021 by Chris Giles

    This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

  • IP Security: Keys to Early Identification of Security Vulnerabilities

    Webinar - Aug 27, 2021 by John Hallman

    In this session we will demonstrate early security verification on a small module of intellectual property (IP) intended for integration into an IC. Using Methodics IPLM by Perforce’s key technology for IP management and OneSpin 360™ formal verification tools, our technical experts will jointly perform the process recently released for public comment in the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard.

  • RDC Overview & Questa RDC Methodology

    Webinar - Aug 21, 2021 by Atul Sharma

    In this session, you will learn more about Reset Domain Crossing problems and methods to address it. Then you will be introduced to the Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR.

  • Should I Kill My Formal Run? Part 1: Formal Run is In-Progress

    Webinar - Aug 20, 2021 by Dr. Jeremy Levitt

    In this session we will show you the information you can use to decide whether to continue or stop the formal job such as how to monitor the formal engines’ “health” in real time and why a given property analysis might be getting stuck.