Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

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VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

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Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

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BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

New Episode!

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

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DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

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New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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Webinar (223)
Intermediate (120)
Beginner (98)
Advanced (5)

223 Results

  • New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

    Webinar - Mar 14, 2024 by Atul Sharma

    In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

  • Comprehensive CXL 3.0 Verification for High-Bandwidth and Low-Latency Connectivity

    Webinar - Feb 21, 2024 by Chris Browy

    In this session, you will learn considerations for exhaustive verification of the CXL interconnect and how the Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early.

  • Functional Verification Workflow for Trusted and Assured Microelectronics

    Webinar - Feb 06, 2024 by John Hallman

    In this session, we will introduce apps that provide advanced automated functional checking, secure data path verification, trustworthiness assessment, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today.

  • Comprehensive PCIe Verification for Bleeding Edge and Mission Critical SoC & IP Designs

    Webinar - Jan 24, 2024 by Luis Rodriguez

    In this session, you will learn design considerations for PCIe 5.0 and 6.0 design IP and how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs.

  • Multi-Die System Verification with UCIe Avery Verification IP

    Webinar - Dec 07, 2023 by Justin Bunnell

    In this session, we will introduce you to Siemens EDA's Verification Portfolio and then deep dive into UCIe Verification IP, discussing its key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP.

  • Prevent Performance Problems with Prompt RTL Profiling

    Webinar - Nov 09, 2023 by Rich Edelman

    Code profiling is a technique to identify performance issues in software code, helping developers understand how code is being executed, and identifying inefficient “hot spots” that are disproportionately impacting the code’s wall-clock run-time and memory usage.

  • Exploring the Multifaceted Landscape of Formal Coverage

    Webinar - Sep 20, 2023 by Nicolae Tusinschi

    In this session, you will recognize that formal coverage serves as a barometer for design quality, pinpointing areas that require further scrutiny to achieve robustness.

  • Breaking the RISC-V Processor Customization Barrier with Formal Verification

    Webinar - Jul 19, 2023 by Sven Beyer

    In this session, you will learn the role that formal has in state-of-the-art processor DV and the QoS processor core verification workflow.

  • Efficient Interconnect Formal Verification for Complex, Large-scale Designs

    Webinar - May 17, 2023 by Nicolae Tusinschi

    In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.

  • Delivering First Silicon Success for Your Next SoC or 3DIC

    Webinar - Apr 25, 2023 by Gordon Allan

    In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.

  • Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

    Webinar - Apr 11, 2023 by Darron May

    In this session, you will learn how you can accelerate your coverage closure using VIQ’s unique predictive and prescriptive data analysis, maximizing your team's efficiency.

  • Continuous Integration (CI) Driving Efficient Program Execution

    Webinar - Mar 28, 2023 by Kevin Campbell

    In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.

  • Introduction to SystemVerilog Assertions

    Webinar - Mar 15, 2023 by Chris Crile

    In this session, you will learn the benefits of using SystemVerilog assertions including; when and where to use assertions, language structure and implementation code examples.

  • Union of SoC Design & Functional Safety Flow

    Webinar - Nov 30, 2022 by Vedant Garg

    In this session, you will learn how Siemens’ safety verification tools and unique methodologies are easy to adopt, and how they accelerate each development phase.

  • Functional Verification Study - 2022

    Webinar - Nov 16, 2022 by Harry Foster

    In this session, Harry Foster highlights the key findings from the 2022 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

  • Questa Design Solutions as a Sleep Aid

    Webinar - Nov 02, 2022 by Vinayak Desai

    In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.

  • CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis

    Webinar - Oct 25, 2022 by Atul Sharma

    In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.

  • Formal and the Next Normal

    Webinar - Oct 19, 2022 by Joe Hupcey

    In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.

  • Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs

    Webinar - Sep 30, 2022 by Martin Rowe

    In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.

  • Questa Lint vs Formal AutoCheck

    Webinar - Jun 15, 2022 by Kevin Campbell

    In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.

  • The Three Pillars of Intent-Focused Insight

    Webinar - Jun 08, 2022 by Harry Foster

    This session reviews the impact of today’s verification crisis, identifies the fundamental problem contributing to this crisis, and then prescribes a solution.

  • Siemens and the US Government - Mitigating Microelectronics Development Challenges

    Webinar - May 10, 2022 by Rich Powlowsky

    In this session, you will learn how Siemens is a full solution provider to the fabless design community, including SoCs and Heterogeneous Integration from concept through GDSII sign off, through to the manufactured wafer and product life cycle.

  • Bringing Model-based Systems Engineering to IC and FPGA Design

    Webinar - May 10, 2022 by Ray Salemi

    In this session, you will learn how international competition has forced the change, how model-based design will change the way the Defense Industrial Base works with the DoD, and what all this means for IC verification.

  • From Model to Implementation with High-Level Synthesis

    Webinar - May 10, 2022 by Russell Klein

    In this session, you will learn how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.

  • Accelerate Learning Curves and Achieve Program Goals Efficiently

    Webinar - May 10, 2022 by Chris Giles

    In this session, you will learn how Questa Design Solutions accelerates development learning and improves and instruments development efficiency by providing design quality insight early, then monitoring throughout development.