Siemens EDA at GOMACTech

March 17th - 20th, 2025 | Pasadena Convention Center

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New Master’s-level Course

Functional Verification of Digital Logic

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IC/ASIC & FPGA Trends

2024 Siemens EDA and Wilson Research Group Functional Verification Study

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Debug Webinar

Faster Debug of Complex Testbenches Using Visualizer

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ISO 26262 Webinar

Wednesday, Mar 12th-8:00 AM PDT

Safety Analysis for Automotive Chips Based on ISO 26262

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Safety & Security Webinar

FPGA Equivalence Checking from RTL to the Bitstream

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SIEMENS Verification Academy

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Webinar (223)
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223 Results

  • Trust but Verify Your IP with Solido Crosscheck

    Webinar - May 10, 2022 by Felipe Schneider

    This session will show Solido Crosscheck as the one-stop-shop solution for IP validation and QA accountability among IP designers and IP integrators.

  • Formal 101 - Fast, Scalable Formal Verification Made Easy

    Webinar - Mar 17, 2022 by Joe Hupcey

    In this session, we will give an overview of how to apply basic abstractions, how to set up & optimize constraints, and where and how to leverage Data Independence & Non-Determinism.

  • Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

    Webinar - Mar 10, 2022 by Buu Huynh

    This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost.

  • Verification of HPC Protocols and Memories

    Webinar - Mar 08, 2022 by Gordon Allan

    In this technical session we focus on the advances in PCI Express generation 6 protocol, and on the Compute Express Link (CXL) protocol.

  • Equivalence Checking for FPGA

    Webinar - Feb 25, 2022 by Martin Rowe

    In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.

  • Achieving High Defect Coverage for Safety Critical and High Reliability Designs

    Webinar - Feb 22, 2022 by Lee Harrison

    In this session you will gain an understanding of how Siemens EDA provides practices, methodologies and integrated tool flows that provides a path to reaching the required manufacturing test quality needed for designs targeted at critically safe and high reliability markets.

  • ‘The Dog Ate my RTL’ Doesn’t Work Anymore

    Webinar - Feb 15, 2022 by Joe Hupcey

    In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

  • Introduction to Questa Lint and CDC for Designers

    Webinar - Jan 25, 2022 by Mathew Yee

    In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.

  • Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal

    Webinar - Dec 20, 2021 by Joe Hupcey

    In this session, you will learn how formal apps can help you address high-value verification challenges; finding deep bugs in complex logic, accelerating code coverage closure, validating low power clock gating and more.

  • Validation of Complex Safety Architectures

    Webinar - Nov 18, 2021 by Vedant Garg

    This session explains the methodology and flow of how to perform an accurate safety analysis, followed by fault simulation on the SoC or IP with a combination of hardware and software safety mechanisms.

  • Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies

    Webinar - Nov 02, 2021 by Kurt Takara

    In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised.

  • CDC Philosophy: The existential questions of constraints, waivers, and truth

    Webinar - Oct 12, 2021 by Kurt Takara

    In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly.

  • Improving Initial RTL Quality

    Webinar - Sep 15, 2021 by Chris Giles

    This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

  • IP Security: Keys to Early Identification of Security Vulnerabilities

    Webinar - Aug 27, 2021 by John Hallman

    In this session we will demonstrate early security verification on a small module of intellectual property (IP) intended for integration into an IC. Using Methodics IPLM by Perforce’s key technology for IP management and OneSpin 360™ formal verification tools, our technical experts will jointly perform the process recently released for public comment in the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard.

  • RDC Overview & Questa RDC Methodology

    Webinar - Aug 21, 2021 by Atul Sharma

    In this session, you will learn more about Reset Domain Crossing problems and methods to address it. Then you will be introduced to the Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR.

  • Should I Kill My Formal Run? Part 1: Formal Run is In-Progress

    Webinar - Aug 20, 2021 by Dr. Jeremy Levitt

    In this session we will show you the information you can use to decide whether to continue or stop the formal job such as how to monitor the formal engines’ “health” in real time and why a given property analysis might be getting stuck.

  • Exploration into Safety Analysis Techniques That Optimize the Safety Workflow

    Webinar - Aug 13, 2021 by Ann Keffer

    In this session, you will gain an understanding of how Siemens EDA provides a methodology that results in achieving a single iteration around costly fault injection, resulting in a more predictable project schedule and an accelerated time-to-certification.

  • UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level

    Webinar - Aug 05, 2021 by Pedram Riahi - Raytheon

    This session is a customer presentation on his experience using the UVMF and Mathworks® integration in block, subsystem, and chip level simulations.

  • Managing Requirements in a Functional Safety Environment

    Webinar - Jul 29, 2021 by Thorsten Stahlberg - Siemens EDA

    In this session, you will learn that Requirements Management in a "Functional Safety" environment can be very challenging. With Polarion ALM you have a comprehensive solution at hand that fully supports you in successfully managing not only the pure requirements themselves but also all related processes.

  • Using Formal Verification in Daily Work

    Webinar - Jul 29, 2021 by Dr. Abdelouahab Ayari - Siemens EDA

    In this session, we will describe some typical formal applications and how the formal results can be integrated with other verification results.

  • Digital Functional Verification for Safety-Critical Automotive Applications

    Webinar - Jul 29, 2021 by Michael Bierl - Siemens EDA

    In this session, you will be shown a coverage driven verification flow based on the Questa platform. You will also learn how a web-based platform helps to finalize the project successfully even in teams spread over multiple locations.

  • CDC Verification: Beyond Structural Analysis

    Webinar - Jul 29, 2021 by Mark Handover

    In this session, we will cover the overall CDC methodology and cover CDC protocols and reconvergence in more details and show what could happen if these steps are skipped.

  • Mitigating the Effects of Random Hardware Faults

    Webinar - Jul 29, 2021 by Dirk Hansen

    Random faults cannot be prevented so the goal there is to sufficiently tolerate them. With random faults you are really just trying to make sure that the product will fail safely when inevitably one of these random hardware faults occurs. In this session we will outline approaches on how to tackle systematic as well as random faults.

  • AMS Functional Verification for Safety-Critical Automotive Applications

    Webinar - Jul 29, 2021 by Sumit Vishwakarma

    In this session, you will learn how Siemens EDA Symphony platform addresses today's nanometer mixed signal verification challenges for safety-critical automotive applications.

  • A Path to Develop Safe ICs - Part 2

    Webinar - Jul 29, 2021 by Stephanie Dournelle, Paul Williams - Siemens EDA

    In this session you will learn that Siemens EDA has developed a platform that allows early collaboration between OEMs and their suppliers. It provides a clear definition of requirements and allows hardware and software functionality to be tested in a virtual environment long before silicon is available.