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Delivering First Silicon Success for Your Next SoC or 3DIC
Webinar - Apr 25, 2023 by Gordon Allan
In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.
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Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data
Webinar - Apr 11, 2023 by Darron May
In this session, you will learn how you can accelerate your coverage closure using VIQ’s unique predictive and prescriptive data analysis, maximizing your team's efficiency.
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Continuous Integration (CI) driving efficient program execution
Webinar - Mar 28, 2023 by Kevin Campbell
In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.
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How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself
Webinar - Mar 18, 2023 by Joon Hong
In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.
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Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Webinar - Mar 16, 2023 by Neil Johnson
In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.
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Introduction to SystemVerilog Assertions
Webinar - Mar 15, 2023 by Chris Crile
In this session, you will learn the benefits of using SystemVerilog assertions including; when and where to use assertions, language structure and implementation code examples.
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Union of SoC Design & Functional Safety Flow
Webinar - Nov 30, 2022 by Vedant Garg
In this session, you will learn how Siemens’ safety verification tools and unique methodologies are easy to adopt, and how they accelerate each development phase.
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Functional Verification Study - 2022
Webinar - Nov 16, 2022 by Harry Foster
In this session, Harry Foster highlights the key findings from the 2022 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
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Questa Design Solutions as a Sleep Aid
Webinar - Nov 02, 2022 by Vinayak Desai
In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
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CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Webinar - Oct 25, 2022 by Atul Sharma
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
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Formal and the Next Normal
Webinar - Oct 19, 2022 by Joe Hupcey
In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.
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Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs
Webinar - Sep 30, 2022 by Martin Rowe
In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.
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Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Webinar - Sep 21, 2022 by Gordon Allan
In this session, we take a look at how to scale your verification capability to match those designs, divide and conquer, and use the right abstractions to equip projects with high quality and faster time-to-market, and to equip design/verification engineers with scalable tools and solutions for verification.
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Questa Lint vs Formal AutoCheck
Webinar - Jun 15, 2022 by Kevin Campbell
In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.
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The Three Pillars of Intent-Focused Insight
Webinar - Jun 08, 2022 by Harry Foster
This session reviews the impact of today’s verification crisis, identifies the fundamental problem contributing to this crisis, and then prescribes a solution.
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Siemens and the US Government - Mitigating Microelectronics Development Challenges
Webinar - May 10, 2022 by Rich Powlowsky
In this session, you will learn how Siemens is a full solution provider to the fabless design community, including SoCs and Heterogeneous Integration from concept through GDSII sign off, through to the manufactured wafer and product life cycle.
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Bringing Model-based Systems Engineering to IC and FPGA Design
Webinar - May 10, 2022 by Ray Salemi
In this session, you will learn how international competition has forced the change, how model-based design will change the way the Defense Industrial Base works with the DoD, and what all this means for IC verification.
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From Model to Implementation with High-Level Synthesis
Webinar - May 10, 2022 by Russell Klein
In this session, you will learn how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.
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Accelerate Learning Curves and Achieve Program Goals Efficiently
Webinar - May 10, 2022 by Chris Giles
In this session, you will learn how Questa Design Solutions accelerates development learning and improves and instruments development efficiency by providing design quality insight early, then monitoring throughout development.
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Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
Webinar - May 10, 2022 by Bob Oden
In this session, you'll learn how the UVM Framework and Questa Verification IP enables testbench creation in a day so the team can focus on creating tests and closing coverage.
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How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification
Webinar - May 10, 2022 by Joe Hupcey
In this session, you will learn about the unique capabilities in Siemens EDA's formal solutions , then share a case study on how automated formal "unreachability" analysis can accelerate overall verification coverage closure via integration with QuestaSim.
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Accelerate Development Using Advanced Debugging Approaches
Webinar - May 10, 2022 by Rich Edelman
In this session, you will learn how Visualizer Debug Environment provides a high-performance, high-capacity, tightly integrated debug environment for Simulation and Emulation.
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Collaborative Verification Management & Coverage Analysis
Webinar - May 10, 2022 by Darron May
In this session, you will learn of the applications which comprise VIQ, which help manage all verification tasks including test plan creation, coverage analysis, regression management, and metric trending.
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Securing the Electronics Development Chain with IC Integrity Solutions
Webinar - May 10, 2022 by John Hallman
In this session we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking for this very complex IC integrity challenge.
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System Level SoC Verification and Validation Using Emulation and Prototype Platforms
Webinar - May 10, 2022 by Vijay Chobisa
This session covers the Veloce Strato+ emulation platform, delivering fast execution speed, full debug visibility, flexible use models, and ease-of-use in models that span the entire range of needs throughout the life of the chip/SoC development process.