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Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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Verification Horizons Blog

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Fremont, CA

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

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Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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Webinar (218)
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218 Results

  • Explore How to Protect Against Data Corruption with Formal Security Verification

    Webinar - Feb 05, 2025 by Nicolae Tusinschi

    In this session, you will learn about the importance of hardware security including; why robust hardware security is fundamental to all security applications, especially as hardware forms the backbone of critical systems and the implications of hardware breaches, which can lead to severe financial, reputational, and operational consequences.

  • Streamlining FPU Verification with an Alternative to C-reference Model Approaches

    Webinar - Jan 22, 2025 by Nicolae Tusinschi

    In this session, you will be introduced to the Questa FPU application, explaining how it can quickly detect design inconsistencies and reduce verification time from months to days (based on an easy setup process).In this session, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation.

  • Unlocking the Power of QuestaSim and Visualizer Integration

    Webinar - Jan 15, 2025 by Justin Royse

    In this session, you will learn how you can get faster simulation runs, smaller simulation databases. We will also cover qrun which simplifies your scripting environment by bringing together compilation, optimization and elaboration into a single command and fewer switches. Then we will cover how you can get better coverage performance using our Next-Gen Coverage engine.

  • Boost Your Verification Productivity with Questa Verification IQ

    Webinar - Nov 21, 2024 by Mark Carey

    In this webinar, you will learn how to implement a collaborative, plan-driven verification process, complemented by a requirement-driven process for complete traceability from requirements to implementation and verification results.

  • Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

    Webinar - Oct 30, 2024 by Kamlesh Mulchandani

    In this session, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.

  • Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs

    Webinar - Sep 11, 2024 by Nicolae Tusinschi

    In this session, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge, providing user-friendly interfaces, significantly reducing verification environment setup time. Optimized for top-tier performance and scalability, Questa Formal VIP AMBA achieves high-efficiency with accurate protocol compliance.

  • The Future of Multi-Die System Verification with UCIe

    Webinar - Aug 21, 2024 by Justin Bunnell

    In this session, you will be introduced to the UCIe protocol with a focus on the latest evolutions of the specification, followed by a deep dive into the key features of Siemens Avery UCIe Verification IP that enable efficient verification of multi-die systems. These include dynamic block-level and System-in-Package (SiP) level testbench creation, intelligent traffic generation, error injection, advanced debug features, and comprehensive performance monitoring.

  • Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim

    Webinar - Jul 24, 2024 by Fan Zhang

    In this session, you will be provided with an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally, we'll delve into QEMU, the open-source system emulator, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow.

  • Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

    Webinar - May 22, 2024 by Farhad Ahmed

    In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

  • Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

    Webinar - Apr 16, 2024 by Rich Edelman

    Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.

  • Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

    Webinar - Mar 27, 2024 by Rick Koster

    This session will describe a reliable formal-based method to manage Xs in GLS. It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator.

  • New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

    Webinar - Mar 14, 2024 by Atul Sharma

    In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

  • Comprehensive CXL 3.0 Verification for High-Bandwidth and Low-Latency Connectivity

    Webinar - Feb 21, 2024 by Chris Browy

    In this session, you will learn considerations for exhaustive verification of the CXL interconnect and how the Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early.

  • Functional Verification workflow for Trusted and Assured Microelectronics

    Webinar - Feb 06, 2024 by John Hallman

    In this session, we will introduce apps that provide advanced automated functional checking, secure data path verification, trustworthiness assessment, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today.

  • Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs

    Webinar - Jan 24, 2024 by Luis Rodriguez

    In this session, you will learn design considerations for PCIe 5.0 and 6.0 design IP and how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs.

  • Multi-Die System Verification with Siemens’s UCIe VIP

    Webinar - Dec 07, 2023 by Justin Bunnell

    In this session, we will introduce you to Siemens EDA's Verification Portfolio and then deep dive into UCIe Verification IP, discussing its key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP.

  • Prevent Performance Problems with Prompt RTL Profiling

    Webinar - Nov 09, 2023 by Rich Edelman

    Code profiling is a technique to identify performance issues in software code, helping developers understand how code is being executed, and identifying inefficient “hot spots” that are disproportionately impacting the code’s wall-clock run-time and memory usage.

  • Exploring the Multifaceted Landscape of Formal Coverage

    Webinar - Sep 20, 2023 by Nicolae Tusinschi

    In this session, you will recognize that formal coverage serves as a barometer for design quality, pinpointing areas that require further scrutiny to achieve robustness.

  • Breaking the RISC-V Processor Customization Barrier with Formal Verification

    Webinar - Jul 19, 2023 by Sven Beyer

    In this session, you will learn the role that formal has in state-of-the-art processor DV and the QoS processor core verification workflow.

  • Efficient Interconnect Formal Verification for Complex, Large-scale Designs

    Webinar - May 17, 2023 by Nicolae Tusinschi

    In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.

  • Delivering First Silicon Success for Your Next SoC or 3DIC

    Webinar - Apr 25, 2023 by Gordon Allan

    In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.

  • Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

    Webinar - Apr 11, 2023 by Darron May

    In this session, you will learn how you can accelerate your coverage closure using VIQ’s unique predictive and prescriptive data analysis, maximizing your team's efficiency.

  • Continuous Integration (CI) driving efficient program execution

    Webinar - Mar 28, 2023 by Kevin Campbell

    In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.

  • How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

    Webinar - Mar 18, 2023 by Joon Hong

    In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.

  • Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

    Webinar - Mar 16, 2023 by Neil Johnson

    In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.