Upcoming Webinar

Simulating AMD’s next-gen Versal Adaptive SoC devices using QuestaSim

Wednesday, July 24th - 8:00 AM US/Pacific

Learn more and Register!

Search Results

Reset All



Show More

Show Less

Content Type



Show More

Show Less

211 Results

  • Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim

    In this session, you will be provided with an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally, we'll delve into QEMU, the open-source system emulator, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow.

  • Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

    In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

  • Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

    Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.

  • Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

    This session will describe a reliable formal-based method to manage Xs in GLS. It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator.

  • New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

    In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

  • Comprehensive CXL 3.0 Verification for High-Bandwidth and Low-Latency Connectivity

    In this session, you will learn considerations for exhaustive verification of the CXL interconnect and how the Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early.

  • Functional Verification workflow for Trusted and Assured Microelectronics

    In this session, we will introduce apps that provide advanced automated functional checking, secure data path verification, trustworthiness assessment, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today.

  • Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs

    In this session, you will learn design considerations for PCIe 5.0 and 6.0 design IP and how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs.

  • Multi-Die System Verification with Siemens’s UCIe VIP

    In this session, we will introduce you to Siemens EDA's Verification Portfolio and then deep dive into UCIe Verification IP, discussing its key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP.

  • Prevent Performance Problems with Prompt RTL Profiling

    Code profiling is a technique to identify performance issues in software code, helping developers understand how code is being executed, and identifying inefficient “hot spots” that are disproportionately impacting the code’s wall-clock run-time and memory usage.

  • Exploring the Multifaceted Landscape of Formal Coverage

    In this session, you will recognize that formal coverage serves as a barometer for design quality, pinpointing areas that require further scrutiny to achieve robustness.

  • Breaking the RISC-V Processor Customization Barrier with Formal Verification

    In this session, you will learn the role that formal has in state-of-the-art processor DV and the QoS processor core verification workflow.

  • Efficient Interconnect Formal Verification for Complex, Large-scale Designs

    In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.

  • Delivering First Silicon Success for Your Next SoC or 3DIC

    In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.

  • Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

    In this session, you will learn how you can accelerate your coverage closure using VIQ’s unique predictive and prescriptive data analysis, maximizing your team's efficiency.

  • Continuous Integration (CI) driving efficient program execution

    In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.

  • How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

    In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.

  • Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

    In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.

  • Introduction to SystemVerilog Assertions

    In this session, you will learn the benefits of using SystemVerilog assertions including; when and where to use assertions, language structure and implementation code examples.

  • Union of SoC Design & Functional Safety Flow

    In this session, you will learn how Siemens’ safety verification tools and unique methodologies are easy to adopt, and how they accelerate each development phase.

  • Functional Verification Study - 2022

    In this session, Harry Foster highlights the key findings from the 2022 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

  • Questa Design Solutions as a Sleep Aid

    In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.

  • CDC and RDC Assist: Applying machine learning to accelerate CDC analysis

    In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.

  • Formal and the Next Normal

    In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.

  • Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs

    In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.