UPCOMING WEBINAR

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific

LEARN MORE & REGISTER.

  1. Body

    Author: Progyna Khondkar - Mentor, A Siemens Business Introduction: The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low-power verification methodology, known as the UPF information model. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low-power. Obviously the information originates from both UPF and HDL objects and their properties are the key components of the UPF information model. Here the UPF objects are UPF power domain, power supply networks, relevant design groups, design models etc.; and the design objects are HDL modules, instances, port, nets etc. The properties of UPF or HDL objects are usually a simple and static information, like the name of the object, the file or line information of the object. However object properties may also contain relatively complex information, like the power states of a power domain. Overwhelmingly for some objects, there are also dynamic properties associated with them. For example the current state of a power states of a power domain, or the current operating voltage value of power supplies of power domains. The UPF 3.0 LRM standardize all these objects and properties as well the access mechanism through Tcl and HDL API. The combined static and dynamic object properties from predefined standards made the UPF information model an attractive resource for extending low-power verification and debugging practices beyond tools, platforms, and verification portfolio specific entities. The UPF information model (UPF IM) is a standard, unique, and unified power management framework (or database) for storing and manipulating UPF and HDL objects and their properties. The model contains information about UPF objects, the design, and various relationships between them in order to comprehensively capture the power intent (i.e., power specification) in a standard form. The motivation for formulating the UPF IM in the LRM is to provide a standard underlying infrastructure model for power management. Obviously the UPF IM allows access (read/write) with a rich set of APIs that consist of predefined UPF or Tcl based query commands and UPF HDL package functions. The objectives of these APIs are to provide a standard interface across tool vendor platforms, which can be used to access all the static and dynamic power management information augmented on a design, resulting from applying UPF on it. These information are for utilizing in power aware (PA) verification, coverage analysis, debugging, and finally for representing the results. So the UPF IM simplifies the PA verification and debugging by providing a standard framework and API access to manipulate the power information. The 1801 language reference manual (LRM) categorically specifies how and when the UPF objects are constructed in a design verification and implementation flow (DVIF), and how information on these objects are presented in the form of properties within the UPF IM. Let us comprehend the UPF object construction mechanism within the UPF IM through the UPF processing phases. Here it is important to explain that a design may accompany Liberty libraries, based on design abstraction; e.g., Gate-level netlist. For such designs, some of the power intent information can be present in Liberty files as attributes (e.g. power, ground, bias pins) and are usually annotated on HDL objects before UPF processing begins. According to the UPF LRM, UPF processing with a design contains the following processing phases. View & Download: Login with your Verification Academy account and read the entire UPF Information Model: The Future of Low-Power Verification Today technical paper.