New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific


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    Author: Mark Peryer - Mentor Graphics Introduction: Almost all electronics systems use memory components, either for storing executable software or for storing data, therefore having accurate memory models available in proven, standards-based libraries is essential to the functional verification process. The models that make up the library should possess specific qualities, and the library itself should deliver a comprehensive solution that supports any type of simulation environment. High fidelity memory models should include: Front door memory protocol interfacesBack door accessAssertionsFunctional coverage monitorsMemory protocol debug supportStandards complianceCompatibility with all major simulatorsOn-the-fly reconfiguration for second source evaluation Mentor Graphics® now offers a new, comprehensive memory Verification IP (VIP) library that embodies all of these qualities and addresses the growing need for accurate memory simulation models. Memory Model Essentials For verification modelling purposes a memory device can be abstracted as a signal-level protocol interface to a storage array. The signal-level interface has to conform to the timing and behavior of the memory protocol, which may be specified in an industry standard, such as the JEDEC JES79-3F standard for DDR3 or, in a specific case, it may be described in a device manufacturer's datasheet. How the storage array is implemented is not directly visible to the user, but for simulation models it is generally implemented using either a SystemVerilog data structure or an optimized C data structure. View & Download: Login to view the Total Recall: What to Look for in a Memory Model Library technical paper.