Featured Presentations from DVCon US 2021

Siemens EDA technology closes the design and verification gap to improve productivity and quality of results.

Catapult® High-Level Synthesis for C-level verification and PowerPro® for power analysis; Questa® for simulation, low-power, VIP, CDC, Formal and support for UVM and Portable Stimulus; Veloce® for hardware emulation and system of systems verification, unified with the Visualizer™ Debug Environment; Tessent™ Embedded Analytics for fast bring-up and system-level functional debug.

Best Paper: 1st Place

Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunting

^{Released on March 24th, 2021}

Authors: Ping Yeung, Mark Eslinger, Jin Hou - Siemens EDA

Overview:

Several companies have used formal verification to perform silicon bug hunting. That is one of the most advanced usages of formal verification.

It is a complex process that includes incorporating multiple sources of information and managing numerous success factors concurrently. In this paper, we will share a “spiral refinement” bug hunt methodology that captures the success factors and guides the deployment of various formal techniques. The objective is to identify the significant challenges and to gradually improve each of the factors so that we can “zero-in” on these critical bugs.

View Recording | Slides | Paper

Best Poster: Third Place

Preventing Glitch Nightmares on CDC Paths: The Three Witches

^{Released on March 26th, 2021}

Authors: Jian-Hua Yan - MediaTekInc; Ping Yeung, Stewart Li & Sulabh-Kumar Khare - Siemens EDA

Overview:

As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability.

Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths. After deployed gate-level CDC on several projects, we had gained more experience. We learned that it is even more critical to verify glitches on the unsynchronized and combinational CDC paths. In this paper, we first explain the glitch problems in various types of CDC paths. Then, we summarize the automatic formal-based glitch detection methodology that we have deployed for a few years.

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Featured Sessions

Trends in Functional Verification

^{Released on March 2nd, 2021}

Author:
Harry Foster - Siemens EDA

Overview:

In 2020 COVID-19 had a negative impact on the global economy, yet the semiconductor market grew larger than expected. This growth in the semiconductor market was driven by the demand for networking, cloud, and computing solutions required to support today’s work-at-home environment. Also in 2020 we witnessed the introduction of 5G mobile devices and the emergence of new infrastructure required to support 5G, all fueling the semiconductor market growth. Today, semiconductor design is experiencing higher levels of integration combined with an increasing amount of new requirements. This is driving complexity beyond levels we have ever seen. Adopting proven solutions to achieve functional correctness has become critical. In this talk Harry will explore today’s functional verification landscape and present the latest industry trends.

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Applying Big Data to Next-Generation Coverage Analysis and Closure

^{Released on March 26th, 2021}

Authors:
Tom Fitzpatrick, Darron May, Thom Ellis, Athira Panicker - Siemens EDA

Overview:

Coverage closure remains the biggest functional verification challenge in our industry. This two-hour technical presentation will establish the need for a next-generation collaborative verification platform, providing enterprise-wide team-based shared coverage analytics and collaborative verification process integration, including lifecycle management integration. We will explore new ways of visualizing coverage data from different verification platforms – including simulation, emulation, FPGA and virtual prototyping and formal verification – to facilitate analytical navigation, and applying advanced analytics, including data mining and machine learning, to help your team identify functional coverage holes and effectively mobilize your verification team to reach coverage closure like never before.

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Papers & Posters

“Bounded Proof” Sign-Off with Formal Coverage

^{Released on March 25th, 2021}

Authors:
Abhishek Anand, Chinyu Chen - Intel; Bathri Subramanian, Joe Hupcey - Siemens EDA

Overview:

When using formal verification on large DUTs, after solving an initial set of provable assertions, it is common to have some remaining assertions which are not proven -- or disproven -- in the course of the analysis. Even though formal couldn’t conclusively verify the expected behavior, the DUT behaviors recorded up until the analysis halted still provides meaningful information. In this paper, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.

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A Novel Variation-Aware Mixed-Signal Verification Methodology to Achieve High-Sigma Variation Coverage at Nanometer Designs

^{Released on March 31st, 2021}

Authors:
Tibi Galambos - Analog Value & Sumit Vishwakarma - Siemens EDA

Overview:

To produce a high yield mixed-signal design today, designers need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at advanced nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical and costly. Design teams are forced to adopt extrapolation methods to shorten the verification cycle and meet time to market demands, at the risk of impacting the design yield. In this paper we discuss a novel ‘variation aware mixed signal verification’ methodology which addresses this problem and delivers high-sigma variation coverage.

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Bringing Reset and Power Domains Together – Confronting UPF Instrumentation Issues

^{Released on March 31st, 2021}

Authors:
Inayat Ali - NXP Semiconductors; Abdul Moyeen, Manish Bhati, Manjunatha Srinivas - Siemens EDA

Overview:

The Unified Power format (UPF) standard enables designers to add power intent for the design. For power management designers typically partition design into power domains. Interactions between these power domains are done through various power control logics like retention logic, isolation logic, level shifters, etc. Designers need to validate that the power control logic does not introduce new multi-clock and multi-reset issues into the design. This paper specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time. This paper also explores the possibilities of enhancing the features of a static verification tool by proposing new rulesets for the tool.

View Recording | Slides | Paper

Primary, Anonymous, or What? The Destiny of Ports From Design Top That Ultimately Are Driven From Off-Chip…

^{Released on March 31st, 2021}

Authors:
Brandon Skaggs - Cypress & Progyna Khondkar - Siemens EDA

Overview:

Top level primary IOs remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications multifold at RTL and gate-level simulations for them. This paper distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation. Our motivation is to create a complete low power verification solution for IOs that will be ultimately driven by off chip resources. The empirical studies in this paper enable us to comprehend the limitations of the current LRM and propose appropriate solutions that are universally applicable in RTL and post synthesis simulations.

View Recording | Slides | Paper

Featured Workshops

Functional Debug: Verification and Beyond

^{Released on March 31st, 2021}

Author:
Hanan Moller - Siemens EDA

Overview:

In this workshop, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture. We will outline a methodology which includes local intelligence inside the SoC to select and communicate off-chip only those monitoring data which are significant and meaningful. In this workshop, we will further discuss the features of functional debug solutions and the benefits they bring throughout the SoC development process.

View Recording | Slides

Early Design And Validation Of An Ai Accelerator’s System Level Performance Using An HLS Design Methodology

^{Released on March 31st, 2021}

Author:
Michael Fingeroff - Siemens EDA

Overview:

This workshop will show how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It will focus on using the open-source MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator. The workshop will demonstrate how pre-hls simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found till very late in a hand-coded RTL design methodology. Finally we will present 2-3 customer case-studies showcasing how these technologies work in conjunction to address our customers HLS design and verification challenges.

View Recording | Slides

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