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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
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      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
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      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured On-Demand Recordings

      • Productive USB4 Verification
      • Equivalence Checking for FPGA
      • Verification of PCIe IP
      • Advancements in UPF 3.1

    • On-Demand Library

      • Three CDC Glitches
      • Optimizing Constraints
      • Fault Campaign for Mixed-Signal
      • Low Power Verification
      • All On-Demand Webinars

    • Recording Archive

      • Preparing for PCIe 6.0: Parts I & II
      • Verification Forum 2021: Automotive Functional Safety
      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Visualizer Debug Environment
      • All Recordings

    • Conferences & WRG

      • Industry Data & Surveys
      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa Basic
      • Questa Advanced
      • Mastering Questa
      • UVM Framework
  • Home
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  • Featured Presentations from DVCon US 2021

Featured Presentations from DVCon US 2021

Siemens EDA technology closes the design and verification gap to improve productivity and quality of results.

Catapult® High-Level Synthesis for C-level verification and PowerPro® for power analysis; Questa® for simulation, low-power, VIP, CDC, Formal and support for UVM and Portable Stimulus; Veloce® for hardware emulation and system of systems verification, unified with the Visualizer™ Debug Environment; Tessent™ Embedded Analytics for fast bring-up and system-level functional debug.

   DVCON US 2021

 

Best Paper: 1st Place

Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunting

Released on March 24th, 2021

Authors: Ping Yeung, Mark Eslinger, Jin Hou - Siemens EDA

Overview:

Several companies have used formal verification to perform silicon bug hunting. That is one of the most advanced usages of formal verification.

   DVCon 2021 Best Paper - 1st Place

It is a complex process that includes incorporating multiple sources of information and managing numerous success factors concurrently. In this paper, we will share a “spiral refinement” bug hunt methodology that captures the success factors and guides the deployment of various formal techniques. The objective is to identify the significant challenges and to gradually improve each of the factors so that we can “zero-in” on these critical bugs.

View Recording | Slides | Paper

Best Poster: Third Place

Preventing Glitch Nightmares on CDC Paths: The Three Witches

Released on March 26th, 2021

Authors: Jian-Hua Yan - MediaTekInc; Ping Yeung, Stewart Li & Sulabh-Kumar Khare - Siemens EDA

Overview:

As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability.

   DVCon 2021 Best Poster - 3rd Place

Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths. After deployed gate-level CDC on several projects, we had gained more experience. We learned that it is even more critical to verify glitches on the unsynchronized and combinational CDC paths. In this paper, we first explain the glitch problems in various types of CDC paths. Then, we summarize the automatic formal-based glitch detection methodology that we have deployed for a few years.

View Recording | Slides | Paper

Featured Sessions

Trends in Functional Verification

Released on March 2nd, 2021

Author:
Harry Foster - Siemens EDA

Overview:

In 2020 COVID-19 had a negative impact on the global economy, yet the semiconductor market grew larger than expected. This growth in the semiconductor market was driven by the demand for networking, cloud, and computing solutions required to support today’s work-at-home environment. Also in 2020 we witnessed the introduction of 5G mobile devices and the emergence of new infrastructure required to support 5G, all fueling the semiconductor market growth. Today, semiconductor design is experiencing higher levels of integration combined with an increasing amount of new requirements. This is driving complexity beyond levels we have ever seen. Adopting proven solutions to achieve functional correctness has become critical. In this talk Harry will explore today’s functional verification landscape and present the latest industry trends.

View Recording

Applying Big Data to Next-Generation Coverage Analysis and Closure

Released on March 26th, 2021

Authors:
Tom Fitzpatrick, Darron May, Thom Ellis, Athira Panicker - Siemens EDA

Overview:

Coverage closure remains the biggest functional verification challenge in our industry. This two-hour technical presentation will establish the need for a next-generation collaborative verification platform, providing enterprise-wide team-based shared coverage analytics and collaborative verification process integration, including lifecycle management integration. We will explore new ways of visualizing coverage data from different verification platforms – including simulation, emulation, FPGA and virtual prototyping and formal verification – to facilitate analytical navigation, and applying advanced analytics, including data mining and machine learning, to help your team identify functional coverage holes and effectively mobilize your verification team to reach coverage closure like never before.

View Recording | Slides

Papers & Posters

“Bounded Proof” Sign-Off with Formal Coverage

Released on March 25th, 2021

Authors:
Abhishek Anand, Chinyu Chen - Intel; Bathri Subramanian, Joe Hupcey - Siemens EDA

Overview:

When using formal verification on large DUTs, after solving an initial set of provable assertions, it is common to have some remaining assertions which are not proven -- or disproven -- in the course of the analysis. Even though formal couldn’t conclusively verify the expected behavior, the DUT behaviors recorded up until the analysis halted still provides meaningful information. In this paper, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.

View Recording | Poster | Paper

 

Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Released on March 25th, 2021

Authors:
Ray Salemi & Tom Fitzpatrick - Siemens EDA

Overview:

This paper will describe pyuvm, a Python-based implementation of IEEE 1800.2 UVM. This library provides all of the familiar UVM building blocks to build modular, reusable verification components and environments, including constrained-random transaction sequences and functional coverage, along with the underlying utilities to provide transaction-level communication between the pyuvm environment and the simulator or emulator.

View Recording | Slides | Paper

 

The Life of a SystemVerilog Variable

Released on March 26th, 2021

Author:
Dave Rich - Siemens EDA

Overview:

The life of a SystemVerilog variable may seem like a mundane topic, but there are nuances that get overlooked leading to issues that are difficult to debug. Some of the most common issues are how and when variables get initialized, how concurrent threads interact with the same variable, and how certain variable lifetimes interact with other SystemVerilog features in terms of performance considerations. This paper presents a background on the different categories of variable lifetimes, what their intended use models are, and how improper usage can be corrected.

View Recording | Slides | Paper

 

Making Your DPI-C Interface A Fast River Of Data

Released on March 31st, 2021

Author:
Rich Edelman - Siemens EDA

Overview:

DPI-C is a powerful way to integrate C code with SystemVerilog. The interface is a simple function or task call, identical to a normal SystemVerilog function or task call. This paper will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.

View Recording | Slides | Paper

Handling Reset Domain Crossing for Designs with Set-Reset Flops

Released on March 31st, 2021

Authors:
Inayat Ali - NXP Semiconductors & Abdul Moyeen - Siemens EDA

Overview:

There are cases where the Reset Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design features where there is more than one asynchronous set/reset controlling a flop. This paper specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming.

View Recording | Slides | Paper | Poster

Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog

Released on March 31st, 2021

Authors:
Mohamed Rayan, Mohamed Samy, Haytham Ashour, Ashraf Salem - Siemens EDA

Overview:

In this paper we provide a proposal for “Generic testing environment for Host controller” using SystemVerilog to mimic stimulus similar to the system level, allowing a thorough testing in an easy to debug environment. A case study is made demonstrating the methodology on two different Small Computer System Interface (SCSI) based host controllers.

View Paper | Poster

 

A Novel Variation-Aware Mixed-Signal Verification Methodology to Achieve High-Sigma Variation Coverage at Nanometer Designs

Released on March 31st, 2021

Authors:
Tibi Galambos - Analog Value & Sumit Vishwakarma - Siemens EDA

Overview:

To produce a high yield mixed-signal design today, designers need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at advanced nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical and costly. Design teams are forced to adopt extrapolation methods to shorten the verification cycle and meet time to market demands, at the risk of impacting the design yield. In this paper we discuss a novel ‘variation aware mixed signal verification’ methodology which addresses this problem and delivers high-sigma variation coverage.

View Recording | Slides | Paper

 

Bringing Reset and Power Domains Together – Confronting UPF Instrumentation Issues

Released on March 31st, 2021

Authors:
Inayat Ali - NXP Semiconductors; Abdul Moyeen, Manish Bhati, Manjunatha Srinivas - Siemens EDA

Overview:

The Unified Power format (UPF) standard enables designers to add power intent for the design. For power management designers typically partition design into power domains. Interactions between these power domains are done through various power control logics like retention logic, isolation logic, level shifters, etc. Designers need to validate that the power control logic does not introduce new multi-clock and multi-reset issues into the design. This paper specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time. This paper also explores the possibilities of enhancing the features of a static verification tool by proposing new rulesets for the tool.

View Recording | Slides | Paper

Primary, Anonymous, or What? The Destiny of Ports From Design Top That Ultimately Are Driven From Off-Chip…

Released on March 31st, 2021

Authors:
Brandon Skaggs - Cypress & Progyna Khondkar - Siemens EDA

Overview:

Top level primary IOs remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications multifold at RTL and gate-level simulations for them. This paper distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation. Our motivation is to create a complete low power verification solution for IOs that will be ultimately driven by off chip resources. The empirical studies in this paper enable us to comprehend the limitations of the current LRM and propose appropriate solutions that are universally applicable in RTL and post synthesis simulations.

View Recording | Slides | Paper

Featured Workshops

Functional Debug: Verification and Beyond

Released on March 31st, 2021

Author:
Hanan Moller - Siemens EDA

Overview:

In this workshop, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture. We will outline a methodology which includes local intelligence inside the SoC to select and communicate off-chip only those monitoring data which are significant and meaningful. In this workshop, we will further discuss the features of functional debug solutions and the benefits they bring throughout the SoC development process.

View Recording | Slides

Early Design And Validation Of An Ai Accelerator’s System Level Performance Using An HLS Design Methodology

Released on March 31st, 2021

Author:
Michael Fingeroff - Siemens EDA

Overview:

This workshop will show how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It will focus on using the open-source MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator. The workshop will demonstrate how pre-hls simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found till very late in a hand-coded RTL design methodology. Finally we will present 2-3 customer case-studies showcasing how these technologies work in conjunction to address our customers HLS design and verification challenges.

View Recording | Slides

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