Featured Tutorials from DVCon 2018 | Verification Academy

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The following papers, posters and tutorials, were featured at DVCon 2018.

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Featured Tutorials

Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips

Videos | Slides

Ellie Burns, Gabriel Chidolue and Guillaume Boillet - Mentor, A Siemens Business

In this tutorial, we will step through a complete low-power methodology, and explore the different types of metrics needed at different phases of the design process. It will cover a new and unique low-power coverage methodology that enables designers to verify and track how well they have tested their power management architecture. It will also show how to track not only metrics for how much power is used in the RTL, but also how much power is still being wasted and has potential to be reduced for IP qualification. Finally, it will step through how to bring real power scenarios testing into both your power measurement and management coverage metrics to provide the final phase of power verification and validation.

How to Stay Out of the News with ISO 26262-Compliant Verification

Videos | Slides

Charles Battikha and Doug Smith - Mentor, A Siemens Business

In this tutorial you will learn:

What are the basics of the ISO 26262 standard as it applies to requirements for electronic design & verification of safety critical products
How to estimate the safety level of a design by defining safety goals, selecting "safety mechanisms", and specifying fault metrics
How today's dynamic, static, and hardware-assisted verification flows can be employed to verify the safety-critical RTL designs, gate-level implementations, and embedded bare-metal software and firmware
Advanced techniques to eliminate large numbers of irrelevant faults without compromising the completeness of the verification, or the safety of the finished product.

Featured Poster Presentations

Reusable UPF: Transitioning from RTL to Gate Level Verification

Abstract
Presentation

Reusable UPF: Transitioning from RTL to Gate Level Verification

Authors:
Durgesh Prasad, Jitesh Bansal and Madhur Bhargava - Mentor, A Siemens Business

Abstract:

United Power Format (UPF) is used in a design to specify the power intent of the design. The UPF file is used at all the stages in the verification starting from RTL verification to GLS to place & route stages however it is often the case that UPF needs to be modified at next verification stage. For example UPF at RTL level needs to be modified to be used at GLS level due to design-hierarchy changes, cell placements and cell connections. This creates problem of managing different UPFs at various stages, checking their equivalence to make sure the consistency. In this paper we want to highlight all the differences between an RTL UPF and a GLS UPF. We would also propose a methodology to write RTL UPF in such a way that minimal changes are required during gate level power verification.

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Comprehensive IP to SoC CDC Verification Using Hybrid Data Model

Abstract
Presentation

A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic

Abstract
Presentation

A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic

Authors:
Priya Viswanathan, Kurt Takara, Chris Kwok, Islam Ahmed - Mentor, A Siemens Business

Abstract:
With the increasing complexity of today's System-on-a-Chip (SoC) designs, reset architectures have also increased in complexity. Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset domain crossing (RDC) paths in large SoC designs. This methodology is a 3-step process that provides a requirements-based approach for RDC design and verification.

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Improving Verification Predictability and Efficiency Using Big Data

Abstract
Presentation

Improving Verification Predictability and Efficiency Using Big Data

Author:
Darron May - Mentor, A Siemens Business

Abstract:
Big Data is a term that has been around for many years. The list of applications for Big Data are endless, but the process stays the same: capture, process and analyze. So why shouldn't this technology help improve your verification process efficiency and predict your next chip sign-off? By providing a Big Data infrastructure, with state of the art technologies, within the verification environment, the combination of all verification metrics allows all resources to be used as efficiently as possible and enables process improvements using predictive analysis. This paper covers the technology, the metrics, and the process, and it will explore a number of techniques enabled by such an infrastructure.

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UVM-FM: Reusable Extension Layer for UVM to Simplify Functional Modeling

Abstract
Presentation

UVM-FM: Reusable Extension Layer for UVM to Simplify Functional Modeling

Authors
Ahmed Kamal - Mentor, A Siemens Business

Abstract:

One of the main challenges in SoC verification is time-to-market pressure, for that reason all verification engineers are looking for new approaches to speed up building and developing their test environments. Universal Verification Methodology (UVM) is the de facto method as it combines many common approaches to standardize the test environment architecture. However, the increase in modern systems complexity introduced new obstacles such as modeling layered protocols. This paper introduces a reusable backward compatible extension layer for the UVM package (UVM-FM), and changes the UVM agent architecture to a network-like topology. UVM-FM solves the communication challenges in the layered protocol modeling process and speeds-up the UVM environment creation in a timely manner. In addition to that, the proposed extension for the UVM package gives more debugging capabilities, which is an important key element.

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