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  • 1 answer
    21 views

    Blockmap

    Hi,

    When using the RUVM assistant, I am wondering if the Block Instance Dimension field in the Register Model spreadsheet can be used to generate arrays of front door access registers to simplify entry/maintenance in the spreadsheet for small blocks of registers. If so what is the correct syntax in the various fields (BlockMap Instance Name, BlockMap Address Offset, etc.) to get this to work correctly and what is the usage syntax in my test code?

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    RUVM Block Instance
    Last Activity 2 hours 45 min ago by tradle
  • 0 answers
    7 views

    is MENTOR AHB VIP support unaligned address

    hi,
    i am using mentor AHB VIP. while i randomize addr ,this vip generate unaligned and aligned addr but according to amba 2.o spec ahb support only aligned address. is this VIP support unaligned address.

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    9 hours 2 min ago - No activity yet
  • 0 answers
    13 views

    uvm macros and read_mem()

    Are we comparing data on two locations in following line?

    `CHECK_SIG(read_mem(x,i+72),21'h140F48,`def);

    Then what is x and i?

    Are there some default methods like in cf_sync(), system_setup(), startup_sync UVM/OVM

    Regards
    cam

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    14 hours 32 min ago - No activity yet
  • 0 answers
    13 views

    Interfacing VIPs

    I would like to configure my Verilog DDR2 controller with QVIP provided DDR2 Memory(TLM) as an AHB slave and test it with AHB master sequences from the AHB example. I have an interface to convert AHB address to DDR2 address space and have implemented the AHB Slave functionality in the Controller.

    At the interface, I want to verify both the AHB Slave functionality and the controller functionality of the DDR2 Controller.

    Could anyone point me to how to use two VIPs in the same environment?

    Thank you

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    QVIP AHB DDR2 Interfacing
    2 days 23 hours ago - No activity yet
  • 0 answers
    14 views

    uvmc for questasim in windows

    why the uvmc lib compile does not work for windows questasim, I installed the gcc-4.2.1-mingw32vc9 on questasim 10.1d ,but the uvmc lib script always report error. do I have to work on linux to connect my sc and sv modules?
    ///////////////
    sccom -$(BITS) \
    -work $(UVMC_LIB) \
    -Wall \
    -g \
    -I$(UVMC_HOME)/src/connect/sc \
    $(UVMC_HOME)/src/connect/sc/uvmc.cpp

    ///////////////

    In file included from ../src/connect/sc/uvmc.h:43,
    from ../src/connect/sc/uvmc.cpp:21:
    ../src/connect/sc/uvmc_connect.h:510: error: expected ',' or '...' before 'struct'

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    3 days 18 hours ago - No activity yet
  • 1 answer
    51 views

    What is the best way to inject error to an interface between transaction

    Hello

    I would like to know what is the most recommanded way to inject error inside the interface BETWEEN transaction.
    In my environment, there is a delay between every transaction sent to the DUT, and during this delay I want to be able to inject perturbation on different fields of the interface.

    I have thought of 2 solutions for this :
    - First : implement my driver so at each clock posedge, if no transaction occure, write wrong value on the interface.
    - Second : create a dedicated sequence that will inject perturbation, with a lock/grab system for the sequence which send the actual transcations.

    Thanks

    Pierre-Antoine

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    uvm error injection
    Last Activity 4 days 6 hours ago by cgales
  • 14 answers
    146 views

    Usage of VMM generator for UVM agent in VMM env

    I wan to communicate vmm xactions with uvm agent in vmm env.
    By converting vmm tranctor data to UVM sequence format and connection VMM channel to tlm port of UVM . It's expected to work .

    Will it possible by direct connecting vmm channel to uvm agent with data pakt conversion?
    Is there any other way to avoid data pkt conversion and doing communication between vmm channel to UVM agent in vmm env?

    Or

    any other better approach from 1staboves ?

    Pls explain with example which will properly understandable.

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    Vmm channel uvm agent tlm port
    Last Activity 5 days 8 hours ago by skumarsamal
  • 1 solution
    79 views

    Why Program Block is not used in UVM ?

    Hi,
    My name is Nitin Mathur and new to UVM. while stduying UVM, I encountered one thing that, test case or test is written in class which is inherited from 'uvm_test' and not written in program block. Program block is used to differentiate between testbench and DUT. By not using program block in UVM, won't it kill the important feature of System Verilog ? How race conditions can be avoided in UVM ?

    Regards,
    Nitin Mathur
    Senior Verification Engineer,
    iGATE Global Solutions

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    Last Activity 5 days 17 hours ago by bpdacha
  • 1 answer
    44 views

    Should we never call _phase methods directly ??

    In the uvm_component.svh base class, for each phase method there is a comment included that "This method should never be called directly".

    // Function: connect_phase
    //
    // The phase implementation method.
    //
    // This method should never be called directly.

    extern virtual function void connect_phase(uvm_phase phase);

    I was just wondering, whether these methods should not be called in environment(driver, monitor, test, etc) directly ? Any Comments ?!

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    UVM phase methods
    Last Activity 6 days 5 hours ago by sridar
  • 0 answers
    30 views

    How to give transactions from the uvm sequences to the vmm environment

    Verification environment is in vmm.I want to create testcases in uvm.Is there any method to give transactions from uvm_sequence to vmm_driver?

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    1 week 11 hours ago - No activity yet
  • 1 answer
    59 views

    Why we are using p_sequencer and m_sequencer?

    Why we are using p_sequencer and m_sequencer?

    What is main purpose of them?

    when and where we should use them?

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    Last Activity 6 days 17 hours ago by Urvish_69
  • 1 answer
    48 views

    coverage sampling method issue.config value not updating

    Hi All,

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    Last Activity 4 days 10 hours ago by gani
  • 2 answers
    70 views

    How to configure monitor from sequencer after item randomization

    Hi
    I need some help with the following issue I have learning the uvm flow. In the environment a uart is under test. I've written a monitor for catching DUT transmit packets. The uart allows programming for the number of data bits, number of stop bits, parity enable and baud rate so before transmitting data the monitor needs to be configured. This is where I am stuck. If I use a fixed configuration then the monitor correctly gets the data and scoreboard checks on the packet work. However when the configuration is randomized then the monitor has no idea of the new configuration so cannot correctly decode the transmit packet. This randomization is done in a virtual sequencer if that's significant.

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    configure monitor random items
    Last Activity 1 week 14 hours ago by andrew dickson
  • 0 answers
    33 views

    Why we are creating a configuration object in test class for passing virtual interface reference to the components(Driver and montior)

    In Module top;
    ...
    actual interface handles are assigned to virtual interface handles by using config_db
    ...
    endmodule

    can we assign the above virtual interface reference to driver and monitor virtual interface handles?

    If not why?

    What is meant by components(driver and monitor) are modular and reusable?

    Why we are creating a configuration object in test class for passing virtual interface reference to the components(Driver and montior)?

    what is main motto of it?

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    1 week 15 hours ago - No activity yet
  • 2 answers
    54 views

    randomization problem of enum in derived sequence item

    hi

    I made a base seq item like this and defined some enums and data items inside it. all data item are registered in factory with `uvm_field

    class eth_rw extends uvm_sequence_item;
....

    and i made another seq item derived from it and registered them

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    Last Activity 1 week 16 hours ago by jie
  • 0 answers
    19 views

    Adding tlp port to uvm_component

    I wan to add a tlp port to uvm_component .
    an any one pls explain wht's tlp ?
    and how to support/add it to ant user created uvm_component .?

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    tlp
    1 week 1 day ago - No activity yet
  • 0 answers
    21 views

    does we need to write seperate register model for TYPE0 and TYPE1 Config space in pcie

    does we need to write seperate register model for TYPE0 and TYPE1 Config space in pcie

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    1 week 2 days ago - No activity yet
  • 1 solution
    42 views

    Sequence not scheduling on a proper sequencer

    Hi,

    I am observing a strange problem in my environment. When driving a sequence on an array of agents. I see that sequence is driven only on first agent twice. What I have done is, I have created an agent and in my env used 2 instances of this. From my test, I have created a sequence and driven this sequence on agent[0] first and when complete(it's blocking), I am again driving this sequence on agent[1]. But somehow, I can see that my sequence runs twice on agent[0] only.

    For debug purpose, I have added a m_sequencer.get_full_name print in the body task of the sequence. This is providing proper value, first print provides me agent[0] and second print provides me agent[1]. But the final task in driver which is being called for the "req" I am sending, I can see this is from agent[0] both the times.

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    sequence sequencer agents
    Last Activity 1 week 2 days ago by skumar
  • 2 answers
    94 views

    How can i connect two sequencers to regmodel

    Hi,
    im having a reg_model in my env.
    And i want to connect it to two sequencers, so i could write function:
    reg_model.register.write
    but this syntax is relevant for one sequencer.
    what can i do if i want to use two sequencers and how can i do it?

    Thanks for any help.

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    uvm registers sequencer
    Last Activity 1 week 2 days ago by sankardr
  • 1 answer
    42 views

    can we creating an object for virtula sequence in UVM Test bench with virtual sequence

    Hi,

    In UVM testbench, we are defining virtual sequence in a class by extending the existing sequence.

    i.e.

    class virtual_sequence extends base_sequence;
    ....
    ...

    endclass

    In a test called "TEST1", I am configuring the above virtual sequence as default sequence by using
    UVM_config_db(this, "...", "virtual_sequence" virtual_sequence ::type_id::get());

    Here my question is we are not created an object for virtual sequence then how can i access it's methods and parameters (get(),type_id) inside of config_db

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    Last Activity 1 week 3 days ago by tfitz
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