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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

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    • Coverage Forum

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      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • Exploring Formal Coverage
      • Processor Customization
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar
    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings
    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - July 2023
      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
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    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
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Ask a Question
UVM
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6795 questions in UVM

  • TITLE
    SOLVED
    REPLIES
    VIEWS
    POSTED
    UPDATED
  • How to pass dynamic data array to lower sequence
    2  
    43  
    5 days 1 hour ago
    by YMNKY  
    2 hours 55 min ago
    by dave_59  
  • How to override or disable uvm_status_e i.e. UVM_HAS_X for specific register or specific task
     
    11  
    8 hours 40 min ago
    by saikittu72  
    8 hours 40 min ago
    No activity yet  
  • Unable to get vertual interface from config_db
    2  
    40  
    1 day 16 hours ago
    by pwe_pwe  
    1 day 11 hours ago
    by Have_A_Doubt  
  • Environment and DUT random configuration
    6  
    71  
    2 days 20 hours ago
    by martin_48  
    1 day 13 hours ago
    by chr_sue  
  • How to calculate TON, TOFF, Time period of a signal
     
    12  
    1 day 21 hours ago
    by Tina025  
    1 day 21 hours ago
    No activity yet  
  • SPI Mode fault feature(MODF) Feature
     
    22  
    1 day 16 hours ago
    by m_v  
    1 day 16 hours ago
    No activity yet  
  • Main_phase and run_phases in uvm TB
    9  
    2,416  
    4 years 3 weeks ago
    by Sv-hustler  
    1 day 17 hours ago
    by chr_sue  
  • connecting the dut signals with interafce signals in the test bench top
    1  
    28  
    2 days 1 hour ago
    by lohithkumar.shivamurthy@tessolve.com  
    1 day 17 hours ago
    by chr_sue  
  • xrun option to run cpf simulation
    1  
    34  
    2 days 12 hours ago
    by kesav_apj  
    2 days 10 hours ago
    by cgales  
  • Issues on Queue at receiver class
    17  
    206  
    1 week 3 days ago
    by Yeptho  
    2 days 21 hours ago
    by chr_sue  
  • Predicting Read Only Register in RAL
     
    26  
    3 days 8 hours ago
    by EELearner  
    3 days 8 hours ago
    No activity yet  
  • grabbing sequencers
    4  
    2,177  
    9 years 3 weeks ago
    by ashishk  
    9 years 2 weeks ago
    by Sailaja  
  • UVC vs VIP vs Agent
    10  
    2,396  
    1 year 5 months ago
    by shekher201778  
    4 days 13 hours ago
    by m_v  
  • buid phase and config db set/get
    2  
    94  
    1 week 2 days ago
    by xfinity  
    1 week 18 min ago
    by chr_sue  
  • Example of writing a reset sequence
     
    23  
    1 week 2 days ago
    by curious_verifier  
    1 week 2 days ago
    No activity yet  
  • Verification of components containing PHY IP
    2  
    88  
    2 weeks 1 day ago
    by DefaultName  
    1 week 2 days ago
    by DefaultName  
  • my randomization is failing
    6  
    169  
    2 weeks 1 day ago
    by Ashishkumar072  
    1 week 3 days ago
    by dave_59  
  • How to override constraint?
    1  
    73  
    1 week 4 days ago
    by 3dlmap  
    1 week 3 days ago
    by dave_59  
  • uvm driver code for valid signal
    2  
    63  
    1 week 4 days ago
    by curious_verifier  
    1 week 4 days ago
    by curious_verifier  
  • I'm getting the value of a variable but not using config_db#()::get(), how?
    3  
    128  
    2 weeks 2 days ago
    by PPK  
    2 weeks 1 day ago
    by dave_59  

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16,850 Questions

50,922 Replies

90,020 Users

Welcome to the Verification Academy Forums.

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