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  • 0 answers
    1 view

    Set/Get register value in register model- illegal location for a hierarchical name (in a package

    Hi,
    I am having reigster model and reference model. I have put the instance of register model in base test testcase .Pass the object in uvm_resource_db so that it could be used in basic sequence and reference model.

    // In uvm_base test case:
    uvm_sequence_spi uvm_seq_spi;
    spi_rm_register spi_rm_h;
    build_phase:
    spi_rm_h = sp_rm_register::type_id::create("spi_rm_h");
    uvm_resource_db #(spi_rm_register)::set("*", "spi_reg_model",spi_rm_h, null);

    run_phase :
    uvm_seq_spi = uvm_sequence_spi::type_id::create("uvm_seq_spi");

    // In base sequence
    class uvm_sequence_spi extends uvm_sequence;
    spi_rm spi_rm_h;

    //Under prebody task:
    if(!uvm_resource_db #(spi_rm_register)::read_by_name(get_full_name(), "spi_reg_model", spi_rm_h);

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    51 min 49 sec ago - No activity yet
  • 1 solution
    4,875 views

    Parameterized Classes

    Hi all,

    I am in the middle of writing a parametrized class, and I hit a road block. Is there a way I can overwrite a parameter in the type_id::create call?

    For example, can I do something similar to this?

    Class A #(int j=10)
    ....
    endclass

    Class B
    A m_a;
    int mode;
    ....
    function void build();
    case(mode)
    0: m_a = A#(7)::type_id::create(...);
    1: m_a = A#(2)::type_id::create(...);
    2: m_a = A#(11)::type_id::create(...);
    default: m_a = A#(4)::type_id::create(...);
    endcase
    endfunction
    endclass

    Any comment is greatly appreciated!

    Thanks,
    Billy

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    Last Activity 8 hours 33 min ago by aming
  • 1 answer
    39 views

    Phase objection

    Hi,

    I want to know from where i need to raise an objection.

    I initially put raise/drop objection in the sequence and i found that to be working.
    I found few examples where people have raised/dropped objection in testcase.

    I tried to do the same, but my testcase ended without even randomizing the set of sequence items.

    Please explain.

    Thanks

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    Last Activity 10 hours 49 min ago by Debjit
  • 1 answer
    22 views

    How can implement reusable uvm_sequence_item based on agent's multiple configuration?

    Hi Everyone ,

    i have defined single agent(UVC) and declared 10 agent objects. The each agent object have separate configuration. Now how can i use each configuration to differentiate 10 uvm_sequence_item corresponding to 10 agents.

    example :

    axi_agent a0,a1,a2;

    data_bus width of a0 = 32 bit ;
    data_bus width of a1 = 64 bit ;
    data_bus width of a2 = 128 bit ;

    whenever i will run a0,a1,a2 agent parallel ,the squencer of agent must pick corresponding uvm_seq-> corresponding uvm_seq_item.

    How can i will get implement reusable agent , seq_item ?

    very advance thanks

    Regards
    kbkdec15

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    Last Activity 15 hours 36 min ago by cgales
  • 1 answer
    20 views

    What is the difference between uvm_config_db and uvm_resource_db ?

    Hi

    I would like to know What is the difference between uvm_config_db and uvm_resource_db ?
    Please let me know the difference between the the two config_db's, when it can be used and how it is used with an example?
    I went through so many articles but it is vague and unclear.can some one point me with the expamples and usage ?

    -Thanks,
    -Raja.

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    Last Activity 15 hours 37 min ago by tfitz
  • 2 answers
    50 views

    Failing to connect analysis port.

    Hi, I am failing to connect an analysis port of sequencer with monitor.

    I've an agent with following member:

    my_sequencer sequencer

    my_sequencer has an analysis port implemented with uvm_analysis_imp_decl

    From my environment, I am trying to connect the analysis port of a monitor with the port declared in my sequencer.

    my_agent.my_monitor.transaction_port.connect(my_agent2.sequencer.rec_port)

    I get a message that "sequencer" is not a class item.

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    Last Activity 19 hours 16 min ago by yaohe
  • 1 answer
    53 views

    What is the recommended way to implement coverage driven verification in UVM (connection between coverage and sequence)?

    Hi,

    When implementing coverage driven verification, how should a sequence get information on one or several covergroups instantiated at different places in the testbench (in objects derived from uvm_subscriber for instance, or from an interface) ?

    We can use hierarchical reference from the test environment to the object where the covergroup is instantiated but, for a better reuse, is there a way to pass a reference to a covergroup through the config DB from the object it is instantianted in and get this reference in the sequence ? or something equivalent ?

    Thank you for your help

    Norbert

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    Last Activity 19 hours 21 min ago by Wanglj
  • 1 answer
    47 views

    Creating protocol transfers

    Hi,

    I am trying to build an AHB vip, just to get hold of the basics of UVM.
    I am finding difficulty in randomizing the various AHB protocol signals. For e.g, I can randomize HBURST type , HSIZE type and the starting address. But how do i randomize or create the HTRANS, HADDR for the same burst type (number of HADDR, HTRANS is going to chnage based on the randomized HBURST type). Also, my HADDR values will change, either incremented by 4 or 8 or etc, base on burst type and HSIZE; similarly the HTRANS values can be BUSY and SEQ for burst transfers whereas NSEQ and IDLE for single transfers.

    I am presently handling such things in the driver by generating a loop for the number of beat transfer as dictated by HBURST, HSIZE type. But i am not sure whether that is the right way. What will be the best way to handle this?

    A sample code will be very helpful.

    Thanks.

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    Last Activity 20 hours 7 min ago by yaohe
  • 2 answers
    84 views

    Unresolved reference to 'debug_connected_to'.

    Hi,

    I got the error while the run design in tb.sv file.

    // File name : tb.sv
    In this class we are connected the all passive mode uvc's.
    So for debugging here i was called the 'debug_connected_to' function. To know the TLM port connection.

    function void end_of_elaboration();
    begin
    uvm_report_info(get_full_name(),"End_of_elaboration of EMIC", UVM_LOW);

    debug_connected_to (); // How to call this function?
    end
    endfunction

    Regards,
    Santhosh

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    Last Activity 1 day 35 min ago by yaohe
  • 2 answers
    27 views

    how to register the module in uvm_callback

    HI,

    how to register the module (not class) in uvm_callback.
    Is it possible to do that?
    because I want to corrupt the module file parameter by using callback. For that we need to register tha callback class in driver file.
    So that time we need to register our callback class file.
    uvm_do_callback(class driver,class callback,task callback);

    in the place of class driver, I have module . So is it possible to place instead of class driver??

    Please provide me an idea about this??

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    Last Activity 1 day 15 hours ago by avi_rohan
  • 0 answers
    10 views

    Is it possible to use interface signal in callback

    Hi,
    Is it possible to corrupt the interface signals using callback?
    Data signals from interface before driven to the DUT, I want to corrupt it.
    is it possible?

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    1 day 16 hours ago - No activity yet
  • 0 answers
    13 views

    Special register(s) with fields based on a mode

    Hi,

    I've been tasked with modeling a register block for a semi-legacy module that includes a register scheme that I have not come across in RAL literature.

    The basic idea is that there exists a register called MODE, say at address 0x0. There are (for example) two registers that "share" the same address, say 0x1, each of which define their own set of fields, some of whom have bit offsets that overlap other "shared" register fields. Depending on how the MODE register is configured, only one interpretation of the SHARED registers is considered "valid".

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    2 days 13 hours ago - No activity yet
  • 1 answer
    47 views

    How can an array element can be randomized to particular value by using inline constraint?

     Hi,

    I have a doubt on randomization of array elements with a particular value by using inline constraint.

    For ex:-
    class A
    rand bit[127:0]array[256];
    endclass

    I want to make most of element's value of an array as '0' and other elements values can be randomized.

    How can do the above operation by using inline constraint.

    May i know which approach is correct?

    this.randomize(array) with {foreach(array[i])
    array[i] dist{'0:=90, [1:((2**(128)-1]):=10};};

    (or)

    foreach(array[i]) begin
    this.randomize(array) with {array[i] dist{'0:=90, [1:((2**(128)-1]):=10};};

    (or)

    is there any approach?

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    Last Activity 3 days 10 hours ago by dave_59
  • 0 answers
    81 views

    raise_objection

    In a uvm_component if I call raise objection twice, do i have to call drop_objection twice?.

    I ran a simulation, where i called raise objection twice and drop objection once. where the simulation ends immediately after the drop objection is called. Is that expected behavior ?

    Regards
    Srinivas

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    Last Activity 3 days 20 hours ago by Logie
  • 1 answer
    237 views

    hanging register test

    Hi All,

    I am new in using UVM registers model. I am trying to integrate my model in the environment. I think I did this as it is described in the cookbook.
    And here is my problem:
    I tried to write and run simple test which just write one register and then read it. But the write_reg task doesn't complete at all. The write operation is done correctly, the registers inside the DUT are written and the driver's item_done() method is called, but it seems that the write_reg is waiting for something. My driver doesn't return response so the adapter's provides_responses is set to 0.
    I look at the UVMKIT libraries and noticed that in uvm_reg_map base class. There are these tasks do_bus_write/do_bus_read and they are waiting for bus_req.end_event.wait_on(). Here is where my test hangs it is waiting for bus_req.end_event.wait_on().

    But I don't know why this is not triggered. Does any of you have an idea why is that so and how to resolve the problem.

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    Last Activity 3 days 22 hours ago by spradhan
  • 1 answer
    72 views

    In UVM sequencers,why p_sequencer is used rather than n_sequencer ?

    Hi all,

    In UVM sequencers,why p_sequencer is used rather than n_sequencer ?
    Can Any one explain me in detail ?

    Regards,
    Ravi Chandra.

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    Last Activity 3 days 23 hours ago by nithyavlsi
  • 1 answer
    40 views

    vsim.wlf file gets deleted automatically at the end of simulation

    Hi Verification Academy Forum Desk,

    As per the subject cited above, I'm facing an unexpected issue at the end of simulation.

    I'm using Questsim 10.0 version. While running my code with this tool, I observed that "the simulator is generating vsim.wlf file". But at the end of the simulation, I found there is no vsim.wlf file. It gets deleted automatically.

    So could you please assist me regarding the above said issue and let me know why it's happening and how can I resolve it.

    Thanks in Advance...

    Regards,
    Partha

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    Last Activity 4 days 17 hours ago by cgales
  • 1 solution
    175 views

    Fatal: (SIGSEGV) Bad handle or reference, Error

    Hi,

    I'm student. And I'm new to the SystemVerilog and UVM. So, forgive me in advance if my question might be basic.
    I try to add "Test" and "Config Database" in my verification environment. When I try to simulate, I face the following error:
    (the error refer to the connect phase of my class.)

    ** Fatal: (SIGSEGV) Bad handle or reference.
    # Time: 0 ns Iteration: 13 Process: /uvm_pkg::uvm_phase::m_run_phases/#FORK#1813_f4e5341 File: Driver.sv
    # Fatal error at Driver.sv

    here is my Driver code:

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    Last Activity 4 days 20 hours ago by Neshagar
  • 0 answers
    45 views

    Reading a text file in UVM

    Hi,
    I have generated a random data for my [1023:0] Memory and I have saved it into a text file. I want to read this textfile into my driver class and I treid using the below command.

    $readmemb("search.txt", Searchmem)

    However I am getting an error. Can I please know if there is any other way to read text file and put back in my Searchmem reg?
    Thanks in advance

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    Last Activity 4 days 21 hours ago by dave_59
  • 1 answer
    59 views

    Recording a Class Variable in Questasim

    Hi,

    If there is any way to dump the class variable in QuestaSim for UVMEnviroment.
    Before we use Cadence to dump all the class variable in UVMEnviroment.
    Similar way if it is possible to dump all the class variable in Questasim.

    Regards
    Elango.V

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    Last Activity 4 days 22 hours ago by ben@SystemVerilog.us