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  • 0 answers
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    capturing transactiopn fron uvm vip (i.e. sequencer,monitor and driver) for vmm score board

    I have a vip in uvm world. It's contain driver, monitor and sequencer.
    I also have score board which sits in vmm world.
    Iwan to send transaction fron monitor to score board which is part of vmm world.
    Is there a way to send transaction from monitor to score board?

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    2 hours 34 min ago - No activity yet
  • 1 solution
    37 views

    DPI-C Mapping data types

    Currently working on verification IP for SPARC V8 using UVM

    I have developed a reference model in C it calculates the result and destination register address based on instruction send from SV which is 32-bit length. so, if I declare in SV as
    bit [31:0]inst;

    and used
    import "DPI-C" function void ref_model(input bit [31:0]inst,output bit [31:0]reg_data,output bit [4:0]reg_add);

    what should the corresponding data type in C, I have tried like this in C
    void ref_model(svBitVecVal* inst,svBitVecVal* reg_data,svBitVecVal* reg_add) // included svdpi.h
    {
    printf("inst=%s\n",inst);
    ....
    }

    when I tried to print inst in C some garbage gets printing also not getting outputs reg_data & reg_add.

    appreciate if any experts help me, thank you.

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    Last Activity 5 hours 13 min ago by N Raghava
  • 1 solution
    21 views

    uvm_layering-1.0 problem with uvm 1.1d

    I want to try uvm_layering-1.0 with uvm 1.1d, but when I run the example design, it will report error like:

    lp_sequencer_port [ILLCRT] It is illegal to create a component ('lp_sequencer_port' under 'simple_e1.sequencer') after the build phase has ended.

    I found out that in uvm_layering_agent.svh , they tried to build the sequencer after build phase and before connect phase. but it's not allowed to build anything in connect phase in uvm1.1d. and simply putting the post_build after the build phase does not work since the handler does not exist.

    Is there any new version of uvm_layering-1.0, or is there efficient way to solve the problem? is the callback working for this?

    the code of the uvm_layering_agent.svh is here.

    //////////////

    function void uvm_layering_agent::build();
    layering_ap = new( $psprintf("%s_ap" , m_layering_name ) , this );

    m_factory = uvm_factory::get();

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    Last Activity 5 hours 25 min ago by tfitz
  • 1 solution
    4,054 views

    Layering Sequence. ILLCRT error from questasim.

    I was trying out sequence layering using uvm_layering-1.0.
    I get the following error when i simulate the code.
    //--------------------
    UVM_FATAL @ 0: u_agent_sequencer_port [ILLCRT] It is illegal to create a component ('u_agent_sequencer_port' under 'uvm_test_top.env.l_agent.seqr') after the build phase has ended.
    //--------------------

    I believe that this package is trying to create a new sequencer_port after the build phase. I am not sure on how to overcome this.

    The following is my example code

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    Last Activity 5 hours 28 min ago by tfitz
  • 1 answer
    16 views

    sequencer and driver

    Can a sequencer be connected to more than one drivers?

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    Last Activity 6 hours 44 min ago by shanbhag_akshay
  • 0 answers
    10 views

    Testing Read only Registers

    Morning all,

    death match with the register abstraction layer continues!

    After giving up on the bit bash sequences (poor uvm implmementation of reserved fields) i have written my own access test.
    I am now curious about testing read only register.

    For example, if we have a version register used to indicate the version of hdl code.
    From a register perspective this would be like holding its inputs at set levels forever and ever. If i was to create a test to ensure the read only capability of the register i would create a backdoor write or poke then a front door read?

    So what if i want to change the read-only register from the other side of the register? These are only status pins or hardcoded pins. Can i use the back door for one cycle?
    I know want to create another uvc just for two or three pins.

    Any thoughts?

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    8 hours 32 min ago - No activity yet
  • 1 answer
    122 views

    What is the difference between uvm_config_db and uvm_resource_db ?

    Hi

    I would like to know What is the difference between uvm_config_db and uvm_resource_db ?
    Please let me know the difference between the the two config_db's, when it can be used and how it is used with an example?
    I went through so many articles but it is vague and unclear.can some one point me with the expamples and usage ?

    -Thanks,
    -Raja.

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    Last Activity 10 hours 42 min ago by rajasravan
  • 1 solution
    57 views

    Simple but complete UVM example

    Hi to All,

    I'm novice to the SV methodology world and would like to try out few example code of UVM.
    I tried to work thru the UVM_1.1 UBUS example bundle but I find it too difficult to understand and
    get hang of various constructs used.

    Is there a better & user friendly example available anywhere which I can use a reference for all my
    future projects on SV-UVM?

    Failed to get a complete example by googling and hence I think this forum is the right place to get this answer.

    Thanks
    /Sachin

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    Last Activity 13 hours 16 min ago by sachinrai
  • 1 answer
    57 views

    UVM Support in Veloce Solo Emulator

    Hi,

    I was wondering if Veloce Solo emulator from Mentor Graphics supports UVM testbench?

    The documentation suggested that Veloce Solo does support OVM but I couldn't find if UVM is supported.
    I guess TBX mode should be able to accommodate UVM testbench as long as the Driver is written as a Transactor and made sure to be synthesizable.

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    Last Activity 21 hours 34 min ago by dave_59
  • 0 answers
    14 views

    test

    module dummy (a,b)
    input a;
    output b;
    initial
    begin
    assign b = a;
    end
    end

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    1 day 5 hours ago - No activity yet
  • 0 answers
    21 views

    Is there a way to see which raise objection is still not dropping?

    Is there a way to see which raise objection is still not dropping?

    I'm asking this question because there are times that my simulation hangs-up and then the reason is because there is an objection that is still not dropping.
    It took me a lot of time to debug it, so maybe there is a faster way to know if an objection is still raised.

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    Last Activity 1 day 6 hours ago by nithyavlsi
  • 0 answers
    33 views

    How to use ralgen in VCS

    I have provided below two registers details in xml file to generate ralf from xml.

    Register Name Register Address Register Width Field Name Field Offset Field Width Field Access Field Reset Value
    reg_SBus_command 0x8000 16 SBus_command 0 8 RW 0
    reg_SBus_command unused 7 8 R 0

    I am using below command to convert xml to ralf in UVM format. It gives error shown below command and generating blank ralf file.

    ralgen -uvm -ipxact2ralf sapphire_reg_sheet.xml
    INTERNAL: Could not find element memoryMaps.

    Can anyone tell me my xml file is correct?
    Is there any other mistake done by me?

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    Last Activity 1 day 9 hours ago by DhavalP
  • 1 answer
    251 views

    hanging register test

    Hi All,

    I am new in using UVM registers model. I am trying to integrate my model in the environment. I think I did this as it is described in the cookbook.
    And here is my problem:
    I tried to write and run simple test which just write one register and then read it. But the write_reg task doesn't complete at all. The write operation is done correctly, the registers inside the DUT are written and the driver's item_done() method is called, but it seems that the write_reg is waiting for something. My driver doesn't return response so the adapter's provides_responses is set to 0.
    I look at the UVMKIT libraries and noticed that in uvm_reg_map base class. There are these tasks do_bus_write/do_bus_read and they are waiting for bus_req.end_event.wait_on(). Here is where my test hangs it is waiting for bus_req.end_event.wait_on().

    But I don't know why this is not triggered. Does any of you have an idea why is that so and how to resolve the problem.

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    Last Activity 1 day 12 hours ago by rancohen
  • 1 answer
    53 views

    How can implement reusable uvm_sequence_item based on agent's multiple configuration?

    Hi Everyone ,

    i have defined single agent(UVC) and declared 10 agent objects. The each agent object have separate configuration. Now how can i use each configuration to differentiate 10 uvm_sequence_item corresponding to 10 agents.

    example :

    axi_agent a0,a1,a2;

    data_bus width of a0 = 32 bit ;
    data_bus width of a1 = 64 bit ;
    data_bus width of a2 = 128 bit ;

    whenever i will run a0,a1,a2 agent parallel ,the squencer of agent must pick corresponding uvm_seq-> corresponding uvm_seq_item.

    How can i will get implement reusable agent , seq_item ?

    very advance thanks

    Regards
    kbkdec15

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    Last Activity 1 day 13 hours ago by kbkdec15
  • 1 answer
    74 views

    Connecting the DUT and the Model to single driver ?

    Hey!

    Is it a good idea to share a single driver between the DUT and the Model ? The model is similar to the DUT at the pin level.
    If I create two instances of the drivers, there is no sync. Since the DUT's driver pops off a transaction with get method and its no longer there on the channel. When Model's driver asks for a transaction, it receives completely new test.

    As a fix, I am using the same driver. Driver instantiates the DUT and the model at the pin level and provides the test stimulus to the both at the same time.
    I am not sure if its a good practice though.

    So how to ensure that the DUT and the model receive the same test stimulus ?
    Would like to know the way its done out there.

    Thanks.

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    Last Activity 2 days 18 hours ago by Wanglj
  • 1 answer
    47 views

    Return struct/string from C to SV

    I have a question

    1# I want to return a structure from c-model to the SV my structure is here
    In SV:

    typedef struct {
      string res_data;
      string res_add;
    }rfi;

    In C:

    typedef struct {
      char res_data[32];
      char res_add[32];
    }rfi;
    

    and imported in SV using
    import "DPI-C" function rfi ref_model(string inst);

    I'm getting an error says "unpacked struct can't be return type"
    So when I use
    In SV:
    typedef struct packed{
    string res_data;
    string res_add;
    }rfi;
    getting error:"string can't be in packed struct"

    2# How to return a string type to SV from C?
    i'm using::
    import "DPI-C" function string ref_model(string inst);
    string result;
    result=ref_model(inst);
    when I print result the simulator(VCS) gets terminating without printing the result...

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    Last Activity 2 days 19 hours ago by dave_59
  • 1 answer
    44 views

    Reference model

    I have a question
    #Which high-level language is better/mostly used to model reference model, any reasons why many reference models are in C?

    appreciate if any experts help me, thank you.

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    Last Activity 2 days 19 hours ago by dave_59
  • 1 answer
    45 views

    Should driver/sequencer class name be different from object name?

    Hi,

    I am facing a problem rekated to driver/sequencer class name.

    If i try to create an object with the same name as that of their class names, I am getting an error. For example:

    class ahbs_driver extends uvm_driver #(ahbs_transaction);
    endclass

    class ahbs_agent extends uvm_agent;
    `uvm_component_utils(ahbs_agent)
    ahbs_driver ahbs_driver;
    .....
    ahbs_driver=ahbs_driver::type_id::create("ahbs_driver",this);
    ....
    endclass

    Above is giving me an error:
    Error-[SV-EEM-SRE] Scope resolution error
    ahbs_agent.sv, 15
    test, "ahbs_driver::type_id::create"
    Target for scope resolution operator does not exist. Token 'ahbs_driver' is
    not a class/package. Originating module 'test'.
    Check that class or package exists with referred token as the name

    But if i change the name of the driver class to ahbs_driver1, the error goes off.

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    Last Activity 3 days 2 hours ago by tfitz
  • 3 answers
    219 views

    Can we disconnect the already connected tlm ports and make a new connection ???

    Hi ,
    I want to disconnect tlm port connection which is established in parent class and make a new connection in child class.

    Thanks
    CB Singh

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    Last Activity 3 days 3 hours ago by dave_59
  • 1 answer
    49 views

    Multi-threaded UVM Testbench

    Is UVM capable of creating a multi-threaded testbench. Here multi-core enabled multi-threading is not questioned.
    And if UVM is capable of such multithreading testbench creation then in what manner? Confused about multi-threading and UVM in the same frame.

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    Last Activity 3 days 3 hours ago by dave_59