Latest UVM topics - Verification Academy

Topic	Replies	Views	Activity
About the UVM category	0	320	January 1, 2023
Why does the RAL read() update the mirrored AND desired register model values? UVM , uvm-ral , Ral-write-and-read-methhods	3	2942	May 6, 2024
How can we verify a memory whose address location is swapped UVM , memory-verification	19	10700	May 5, 2024
Uvm_sequencer usage UVM	2	23	May 5, 2024
Seq_item_port driver-sequencer - communication issue	2	24	May 5, 2024
UVM Monitor the interface output, don't use the driver transaction - understanding this training recommendation UVM , uvm-driver-monitor-transaction	2	146	May 4, 2024
While i am using backdoor access for memory model i am able to writing the data into memory while reading the data from back door throug uvm ral i am getting error as either path is invalid or you dont have PLI/ACC visibility for that object UVM	1	23	May 4, 2024
Overriding UVM_NONE messages UVM-Reporting	4	25	May 4, 2024
Coverage collector or subscriber usage UVM , Coverage	0	21	May 4, 2024
Overriding a parameter UVM , parameter-override-class	9	14745	May 1, 2024
Uvm sequence body does not start after completion of base sequence pre_body	3	34	May 1, 2024
Uvm_reg_data_t constraint randomization	2	34	May 1, 2024
Analysis Port Write functionality analysis-port , analysis-export	1	23	April 30, 2024
How to cover unsigned int SystemVerilog , UVM , Coverage	1	46	April 30, 2024
Clarifications about uvm_config db performance	3	59	April 26, 2024
How to set the config_db multiple times? UVM	8	4699	April 26, 2024
Can we use tlm ports if so many componemts are there in sequence ordered defined like	3	38	April 25, 2024
What could be the reason for infinite loop in our code when dealing with sequence and driver	1	35	April 24, 2024
Register mirrored value should update until an event happens in temporal domain	1	28	April 25, 2024
Whether to use TLM ports or class object set in the uvm_config_db	4	41	April 24, 2024
Hierarchical uvm_reg_block add hdl path	0	32	April 24, 2024
Basic rule to use assertion in UVM assertion	1	47	April 23, 2024
Skipping a register field from comparison with RAL RAL , uvm_ral , RAL-UVM	5	63	April 23, 2024
Uvm_hdl_read using macro for string path	1	26	April 22, 2024
If virtual sequencer contain a source sequencer and and destination sequencer and in test I am calling seq.start(envh.v_seqrh) then how ill the tool know to start the sequences on source sequencer or destination sequencer	2	43	April 22, 2024
Using uvm_config_db to register binded interfaces UVM	4	56	April 21, 2024
Confusing UVM_ERROR in uvm_reg_bit_bash_seq UVM , uvm_reg_bit_bash	4	1929	April 19, 2024
How to create array of agent in environment with UVMF yaml UVMF	1	97	April 19, 2024
A better way of getting response back to a waiting sequence?	2	64	April 18, 2024
** Error: /vobs/ss_restart_vseq.sv(714): 'pass_ssr_vseq' is not a task name UVM	3	42	April 18, 2024