I have following code illustrating the idea I want to achieve:
module tb();
dut_wrap dut_wrap_1();
dut_wrap dut_wrap_2();
bind dut_wrap dut_val_for_bind dut_val();
endmodule
module dut _wrap;
logic [1:0] my_in_port;
logic [2:0] my_out_port;
dut dut(.*);
endmodule
module dut(input logic [1:0] my_in_port, output logic [2:0] my_out_port);
//Do your magic
endmodule
module dut_val_for_bind();
import uvm_pkg::*;
dut_ifc dut_if();
assign dut_wrap.my_in_port = dut_if.my_in_port;
assign dut_if.my_out_port = dut_wrap.my_out_port;
initial begin
string this_inst_name = $sformatf("%m");
uvm_config_db#(virtual dut_ifc)::set(null, this_inst_name, "DUT_IFC", dut_if);
end
endmodule
Now, in some component elsewhere, let’s say I want to retrieve the interface by finding it via regular expression like this:
virtual dut_ifc dut_if_1;
virtual dut_ifc dut_if_2;
uvm_config_db#(virtual dut_ifc)::get(null, ".\*dut_wrap_1.\*, "DUT_IFC", dut_if_1);
uvm_config_db#(virtual dut_ifc)::get(null, ".\*dut_wrap_2.\*, "DUT_IFC", dut_if_2);
The problem is that when calling get, then UVM is not matching the regex above within the resource scope, but doing opposite considering the second argument to set as regex and trying to match it against the second argument to get.
So this UVM approach is totally make sense when the intent is top-down setting (i.e. top component setting resource via regular expression to match all the sub-components that will get with their respective scope).
In the above method, at point of interface registration you don’t have to know exactly the topology of your uvm_env and target the interface to there, since this make the env and interface pretty much coupled and if I want to make a relocatable val like I try to do above then I must overcome the obstacle of getting the interface by DUT hierarchy.
Appreciate your ideas here.
Thanks,
Eliran.